Assignment of Assignor's Interest

Recorded: 2008-06-19 Pages: 5

Assignor

CLEAR SHAPE TECHNOLOGIES, INC.

Executed: 2008-06-04

Assignee

CADENCE DESIGN SYSTEMS, INC.

2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134-1931

Covered Property (1)

Timing, Noise, and Power Analysis of Integrated Circuits

Patent: 8,225,248 →

Application: 11/588,095 →

Publication: US 2007/0094623

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.