IP Library Assignment 021145/0353
Patent Assignment
Reel/Frame 021145/0353

Assignment of Assignor's Interest

Recorded: 2008-06-20 Pages: 18
Assignor
Assignee
SYNOPSYS, INC., A DELAWARE CORPORATION
700 E. MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties (15)
Method and Apparatus for Parallel Carry Chains
Patent: 7,836,417 →
Application: 11/388,326 →
Incremental Modification of Instrumentation Logic
Patent: 8,205,186 →
Application: 11/400,590 →
Method and System for Debugging an Electronic System
Patent: 7,506,286 →
Application: 11/417,355 →
Publication: US 2006/0195822
Method and Apparatus for Automated Synthesis of Multi-Channel Circuits
Patent: 7,640,519 →
Application: 11/491,437 →
Publication: US 2006/0265685
Methods and Apparatuses for Reset Conditioning in Integrated Circuits
Patent: 7,594,211 →
Application: 11/601,411 →
Method and Apparatus for Circuit Design and Retiming
Patent: 7,802,213 →
Application: 11/605,554 →
Publication: US 2007/0074139
Method and Apparatus for Automated Circuit Design
Patent: 8,151,228 →
Application: 11/637,360 →
Publication: US 2007/0089074
Power and Ground Shield Mesh to Remove Both Capacitive and Inductive Signal Coupling Effects of Routing in Integrated Circuit Device
Patent: 7,436,008 →
Application: 11/698,330 →
Publication: US 2007/0120261
Method and Apparatus for Automated Synthesis of Multi-Channel Circuits
Patent: 7,765,506 →
Application: 11/700,685 →
Publication: US 2007/0174794
Methods and Systems for Optimizing Designs of Integrated Circuits
Patent: 7,873,930 →
Application: 11/726,777 →
Publication: US 2007/0240091
Method and System for Debugging Using Replicated Logic and Trigger Logic
Patent: 7,665,046 →
Application: 11/732,784 →
Publication: US 2007/0186195
Method and Apparatus for Circuit Partitioning and Trace Assignment in Circuit Design
Patent: 7,844,930 →
Application: 11/762,024 →
Publication: US 2007/0234257
Hardware-Based Hdl Code Coverage and Design Analysis
Patent: 7,836,416 →
Application: 11/786,865 →
Publication: US 2007/0198959
Methods and Apparatuses for Designing Multiplexers
Patent: 7,730,438 →
Application: 11/809,613 →
Publication: US 2008/0301608
Enhanced Hardware Debugging with Embedded Fpgas in a Hardware Description Language
Patent: 7,827,510 →
Application: 11/809,700 →
Related Assignments (7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 7, 2006
From: LAROUCHE, MARIO
To: SYNPLICITY, INC.
Reel/Frame 017749/0093 →
Assignment of Assignor's Interest Jan 30, 2007
From: OKTEM, LEVENT; MCELVAIN, KENNETH S.
To: SYNPLICITY, INC.
Reel/Frame 019045/0847 →
Assignment of Assignor's Interest Feb 14, 2007
From: TIAN, BING; MCELVAIN, KENNETH S.
To: SYNPLICITY, INC.
Reel/Frame 018909/0936 →
Assignment of Assignor's Interest May 31, 2007
From: MCELVAIN, KENNETH S.
To: SYNPLICITY, INC.
Reel/Frame 019425/0230 →
Assignment of Assignor's Interest Jun 14, 2007
From: VUJKOVIC, JOVANKA CIRIC; MCELVAIN, KENNETH S.
To: SYNPLICITY, INC.
Reel/Frame 019454/0598 →
Assignment of Assignor's Interest Mar 17, 2008
From: SCHUBERT, NILS ENDRIC; MCELVAIN, KENNETH S.; BEARDSLEE, JOHN MARK; LAROUCHE, MARIO
To: SYNPLICITY, INC.
Reel/Frame 020681/0015 →
Assignment of Assignor's Interest Feb 16, 2010
From: SYNPLICITY, LLC
To: SYNOPSYS, INC.
Reel/Frame 023943/0038 →