Method and apparatus for automated synthesis of multi-channel circuits
View Patent ↗Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a fewer quantity of time-shared instances of the logical block. The plurality of the instances in the first design is replaced with the fewer time-shared instances in the second design. The time-shared instances in the second design have elements to time multiplex the internal states.
1. A method to design a system, the method comprising:
receiving a first design of a system having a plurality of first instances of a logical block to perform logical operations, wherein the first instances have internal states; and
automatically, through a processor, generating a second design for the system having a time-shared instance of the logical block, wherein the time-shared instance replaces the plurality of the first instances of the logical block in the first design, wherein the time-shared instance has first elements configured to time multiplex operations associated with the internal states of the first instances.
2. The method of claim 1 , wherein the automatically transforming further includes mapping the first elements to the internal states.
3. The method of claim 1 , wherein the first elements include memory elements.
4. The method of claim 1 , wherein the first elements include a cascade of multiple shifting sequential elements.
5. The method of claim 1 , wherein an internal state of the plurality of the first instances includes a memory element.
6. The method of claim 1 , wherein an output of the logical block depends on an internal state.
7. The method of claim 1 , wherein the system has a single channel.
8. The method of claim 1 , wherein the automatically transforming further includes
generating a folding counter to output a folding signal; and
generating one or more switches to provide time-multiplexed signals based on the folding signal.
9. The method of claim 1 , wherein the first instances are coupled sequentially.
10. The method of claim 1 , wherein the logic block includes a finite impulse response filter.
11. The method of claim 1 , wherein the logic block includes a multiply and accumulate operator.
12. The method of claim 1 , wherein the first design of the system further includes one or more instances of another logical block without an internal state.
13. A machine-readable medium storing data that, when accessed by a digital processing system, cause the system to perform operations, comprising:
receiving a first design of a system having a plurality of first instances of a logical block to perform logical operations, wherein the first instances have internal states; and
automatically, through a processor, generating a second design for the system having a time-shared instance of the logical block, wherein the time-shared instance replaces the plurality of the first instances of the logical block in the first design, wherein the time-shared instance has first elements configured to time multiplex operations associated with the internal states of the first instances.
14. The machine-readable medium of claim 13 , wherein the automatically transforming further includes mapping the first elements to the internal states.
15. The machine-readable medium of claim 13 , wherein the first elements include memory elements.
16. The machine-readable medium of claim 13 , wherein the first elements include a cascade of multiple shifting sequential elements.
17. The machine-readable medium of claim 13 , wherein an internal state of the plurality of the first instances includes a memory element.
18. The machine-readable medium of claim 13 , wherein an output of the logical block depends on an internal state.
19. The machine-readable medium of claim 13 , wherein the system has a single channel.
20. The machine-readable medium of claim 13 , wherein the automatically transforming further includes
generating a folding counter to output a folding signal; and
generating one or more switches to provide time-multiplexed signals based on the folding signal.
21. The machine-readable medium of claim 13 , wherein the first instances are coupled sequentially.
22. The machine-readable medium of claim 13 , wherein the logic block includes a finite impulse response filter.
23. The machine-readable medium of claim 13 , wherein the logic block includes a multiply and accumulate operator.
24. The machine-readable medium of claim 13 , wherein the first design of the system further includes one or more instances of another logical block without an internal state.
25. A digital processing system, comprising:
means for receiving a first design of a system having a plurality of first instances of a logical block to perform logical operations, wherein the first instances have internal states; and
means for automatically, generating a second design for the system having a time-shared instance of the logical block, wherein the time-shared instance replaces the plurality of the first instances of the logical block in the first design, wherein the means for automatically generating includes a processor, wherein the time-shared instance has first elements configured to time multiplex the operations associated with internal states of the first instances.
26. The system of claim 25 , wherein the means for automatically transforming further includes mapping the first elements to the internal states.
27. The system of claim 25 , wherein the first elements include memory elements.
28. The system of claim 25 , wherein the first elements include a cascade of multiple shifting sequential elements.
29. The system of claim 25 , wherein an internal state of the plurality of the first instances includes a memory element.
30. The system of claim 25 , wherein an output of the logical block depends on an internal state.
31. The system of claim 25 , wherein the system has a single channel.
32. The system of claim 25 , wherein the means for automatically transforming further includes
means for generating a folding counter to output a folding signal; and
means for generating one or more switches to provide time-multiplexed signals based on the folding signal.
33. The system of claim 25 , wherein the first instances are coupled sequentially.
34. The system of claim 25 , wherein the logic block includes a finite impulse response filter.
35. The system of claim 25 , wherein the logic block includes a multiply and accumulate operator.