Patent Assignment
Reel/Frame 021157/0512
Assignment of Assignor's Interest
Recorded: 2008-06-26
Pages: 6
Assignors
MOE, MATTHEW D.
Executed: 2008-06-24
PILEGGI, LAWRENCE T.
Executed: 2008-06-24
ROVNER, VYACHESLAV V.
Executed: 2008-06-24
HERSAN, THIAGO
Executed: 2008-06-24
MOTIANI, DIPTI
Executed: 2008-06-24
KHETERPAL, VEERBHAN
Executed: 2008-06-24
Assignee
PDF SOLUTIONS, INC.
333 W. SAN CARLOS STREET, SUITE 700, SAN JOSE, CALIFORNIA, 95110
Covered Property
(1)
Method and System for Grouping Logic in an Integrated Circuit Design to Minimize Number of Transistors and Number of Unique Geometry Patterns
Patent:
7,827,516 →
Application:
11/969,214 →
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.