Patent Assignment
Reel/Frame 070893/0428
Security Interest
Recorded: 2025-04-21
Pages: 53
Assignor
PDF SOLUTIONS, INC.
Executed: 2025-03-07
Assignee
WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
P.O. BOX 760776, MAC T7422-012, SAN ANTONIO, TEXAS, 78245
Covered Properties
(152)
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Via Open Configured Fill Cells, and the Second DOE Including Stitch Open Configured Fill Cells
Application:
15/634,176 →
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Merged-Via Open Configured Fill Cells, and the Second DOE Including Stitch Open Configured Fill Cells
Application:
15/635,312 →
Integrated Circuit Containing First and Second DOEs of Standard Cell Compatible, NCEM-Enabled Fill Cells, with the First DOE Including Snake Open Configured Fill Cells, and the Second DOE Including Stitch Open Configured Fill Cells
Application:
15/635,524 →
Domain-Based Search Engine
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One via-Chamfer Short or Leakage, Where Such Measurements Are Obt
Application:
16/020,345 →
IC With Test Structures Embedded Within A Contiguous Standard Cell Area
Application:
16/146,788 →
Cells for Therapy of the Heart
Application:
16/147,775 →
Publication:
US 2019/0100727
Wafer Bin Map Based Root Cause Analysis
Time-Series Segmentation and Anomaly Detection
Application:
18/527,156 →
Publication:
US 2024/0184283
Oportunistic Placement of Ic Test Strucutres in Areas Otherwise Used for Filler Cells, Decap Cells, and/or Dummy Fill, as Well as Product Ic Chips Containing Same
Application:
14/038,799 →
Opportunistic Placement of Ic Test Strucutres and/or E-Beam Target Pads in Areas Otherwise Used for Filler Cells, Tap Cells, Decap Cells, Scribe Lines, and/or Dummy Fill, as Well as Product Ic Chips Containing Same
Application:
14/303,578 →
Opportunistic Placement of Ic Test Strucutres and/or E-Beam Target Pads in Areas Otherwise Used for Filler Cells, Tap Cells, Decap Cells, Scribe Lines, and/or Dummy Fill, as Well as Product Ic Chips Containing Same
Application:
14/612,841 →
Publication:
US 2015/0270181
Evaluating a Surface Microstructure
Application:
18/487,960 →
Publication:
US 2024/0127420
EMBEDDED SYSTEM TO CHARACTERIZE BTI DEGRADATION EFFECTS IN MOSFETs
Patent:
12,416,663 →
Application:
18/385,896 →
Use of Layout Analysis to Enable Efficient and Effective Random Defect Inspection Using a Vector-Mode E-Beam Inspection Machine
Application:
18/829,227 →
Publication:
US 2025/0085234
Sequenced Approach for Determining Wafer Path Quality
Application:
19/004,177 →
Publication:
US 2025/0138505
Systems, Devices, and Methods for Aligning a Particle Beam and Performing a Non-Contact Electrical Measurement on a Cell and/or Non-Contact Electrical Measurement Cell Vehicle Using a Registration Cell
IC With Test Structures Embedded Within A Contiguous Standard Cell Area
Patent:
10,777,472 →
Application:
16/147,631 →
Security Agent
On-Chip Capacitance Measurement for Memory Characterization Vehicle
Patent:
10,096,378 →
Application:
15/441,002 →
Method for Automatically Determining Proposed Standard Cell Design Conformance Based Upon Template Constraints
Patent:
10,102,330 →
Application:
15/395,709 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of a Resistance Through a Stitch, Where Such Measurements Are Obtained by Scanning a Pad Comprised of at Least Three Parallel Conductive Stripes Using a Moving Stage with Beam Deflection to Account for Motion of the Stage
Patent:
10,199,283 →
Application:
15/857,691 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtainedfrom Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Chamfer Short Test Areas
Patent:
10,199,284 →
Application:
15/936,825 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Via Open Test Areas
Patent:
10,199,285 →
Application:
15/937,356 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Corner Short Test Areas
Patent:
10,199,286 →
Application:
15/942,470 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Via Open Test Areas
Patent:
10,199,287 →
Application:
15/942,473 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Side-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Side-to-Side Short, Corner Short, and Via Open Test Areas
Patent:
10,199,288 →
Application:
15/942,483 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Chamfer Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Chamfer Short, Corner Short, and Via Open Test Areas
Patent:
10,199,289 →
Application:
15/942,485 →
Method For Processing A Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative Of At Least One Tip-To-Tip Short Or Leakage, At Least One Tip-To-Side Short Or Leakage, And At Least One Side-To-Side Short Or Leakage, Where Such Measurements Are Obtained From Cells With Respective Tip-To-Tip Short, Tip-To-Side Short, And Side-To-Side Short Test Areas, Using A Charged Particle-Beam Inspector With Beam Deflection To Account For Motion Of The Stage
Patent:
10,199,290 →
Application:
16/019,942 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Chamfer Short Test Areas
Patent:
10,199,293 →
Application:
15/937,182 →
Method For Processing A Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative Of At Least One Side-To-Side Short Or Leakage, At Least One Via-Chamfer Short Or Leakage, And At Least One Corner Short Or Leakage, Where Such Measurements Are Obtained From Cells With Respective Side-To-Side Short, Via-Chamfer Short, And Corner Short Test Areas, Using A Charged Particle-Beam Inspector With Beam Deflection To Account For Motion Of The Stage
Patent:
10,199,294 →
Application:
16/024,856 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Corner Short Test Areas
Patent:
10,211,111 →
Application:
15/936,934 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Side-to-Side Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Side-to-Side Short Test Areas
Patent:
10,211,112 →
Application:
15/936,759 →
Process for Making Ics from Standard Logic Cells That Utilize Ts Cut Mask(S) and Avoid Dfm Problems Caused by Closely Spaced Gate Contacts and Tscut Jogs
Patent:
10,263,011 →
Application:
15/712,723 →
Advanced Manufacturing Insight System for Semiconductor Application
Patent:
10,268,562 →
Application:
15/469,352 →
Method For Processing A Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative Of At Least One Tip-To-Tip Short Or Leakage, At Least One Via-Chamfer Short Or Leakage, And At Least One Corner Short Or Leakage, Where Such Measurements Are Obtained From Cells With Respective Tip-To-Tip Short, Via-Chamfer Short, And Corner Short Test Areas, Using A Charged Particle-Beam Inspector With Beam Deflection To Account For Motion Of The Stage
Patent:
10,290,552 →
Application:
16/024,054 →
Direct Probing Characterization Vehicle for Transistor, Capacitor and Resistor Testing
Patent:
10,380,305 →
Application:
15/273,545 →
Direct Access Memory Characterization Vehicle
Patent:
10,410,735 →
Application:
15/441,016 →
Process Control Techniques for Semiconductor Manufacturing Processes
Characterization Vehicles for Printed Circuit Board and System Design
Test Structures and Method for Electrical Measurement of Finfet Fin Height
Patent:
10,529,631 →
Application:
15/269,854 →
Method for Manufacturing a Semiconductor Product Wafer
Standard Cell Design Conformance Using Boolean Assertions
Patent:
10,565,344 →
Application:
16/205,875 →
Process for Making Semiconductor Dies, Chips, and Wafers Using In-Line Measurements Obtained From DOEs of NCEM-enabled Fill Cells
Patent:
10,593,604 →
Application:
15/090,267 →
IC Chips Containing a Mixture of Standard Cells Obtained From an Original Set of Design Rules and Enhanced Standard Cells that are a Substantially Uniform Variant of the Original Set of Design Rules and Methods for Making the Same
Patent:
10,622,344 →
Application:
15/644,081 →
Method for Applying Charge-Based-Capacitance-Measurement with Switches Using Only Nmos or Only Pmos Transistors
Patent:
10,641,804 →
Application:
15/269,843 →
Passive Array Test Structure for Cross-Point Memory Characterization
Patent:
10,643,735 →
Application:
16/033,156 →
Failure Detection for Wire Bonding in Semiconductors
Direct Memory Characterization Using Periphery Transistors
Patent:
10,679,723 →
Application:
16/211,545 →
Method and Apparatus for Direct Testing and Characterization of a Three Dimensional Semiconductor Memory Structure
Patent:
10,768,222 →
Application:
15/997,411 →
Selective Inclusion/Exclusion of Semiconductor Chips in Accelerated Failure Tests
IC With Test Structures Embedded Within A Contiguous Standard Cell Area
Patent:
10,777,472 →
Application:
16/147,631 →
Snap-To Valid Pattern System and Method
Patent:
10,803,221 →
Application:
15/695,933 →
Test Structures for Measuring Silicon Thickness in Fully Depleted Silicon-on-Insulator Technologies
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Corner Short, and Via Open Test Areas
Patent:
10,854,522 →
Application:
15/942,475 →
Characterization Vehicles for Printed Circuit Board and System Design
IC With Test Structures And E-Beam Pads Embedded Within A Contiguous Standard Cell Area
Patent:
10,978,438 →
Application:
16/458,042 →
Ic with Test Structures and E-Beam Pads Embedded Within a Contiguous Standard Cell Area
Patent:
11,018,126 →
Application:
16/458,082 →
Semiconductor Yield Prediction
Failure Detection and Classsification Using Sensor Data and/or Measurement Data
Generating Robust Machine Learning Predictions for Semiconductor Manufacturing Processes
IC With Test Structures And E-Beam Pads Embedded Within A Contiguous Standard Cell Area
Patent:
11,075,194 →
Application:
16/458,088 →
IC With Test Structures And E-Beam Pads Embedded Within A Contiguous Standard Cell Area
Patent:
11,081,476 →
Application:
16/458,085 →
IC With Test Structures And E-Beam Pads Embedded Within A Contiguous Standard Cell Area
Patent:
11,081,477 →
Application:
16/458,087 →
IC With Test Structures And E-Beam Pads Embedded Within A Contiguous Standard Cell Area
Patent:
11,107,804 →
Application:
16/458,095 →
Maintenance Scheduling for Semiconductor Manufacturing Equipment
Predicting Die Susceptible to Early Lifetime Failure
Methods for Aligning a Particle Beam and Performing a Non-Contact Electrical Measurement on a Cell Using a Registration Cell
Methods for Performing a Non-Contact Electrical Measurement on a Cell, Chip, Wafer, Die, or Logic Block
Systems, Devices, and Methods for Aligning a Particle Beam and Performing a Non-Contact Electrical Measurement on a Cell and/or Non-Contact Electrical Measurement Cell Vehicle Using a Registration Cell
Anomalous Equipment Trace Detection and Classification
Pattern-Enhanced Spatial Correlation of Test Structures to Die Level Responses
Predicting Equipment Fail Mode from Process Trace
Systems, Devices, and Methods for Performing a Non-Contact Electrical Measurement on a Cell, Non-Contact Electrical Measurement Cell Vehicle, Chip, Wafer, Die, or Logic Block
Automatic Window Generation for Process Trace
Wafer Bin Map Based Root Cause Analysis
Rational Decision-Making Tool for Semiconductor Processes
Abnormal Wafer Image Classification
Die Level Product Modeling Without Die Level Input Data
Machine Learning Variable Selection and Root Cause Discovery by Cumulative Prediction
Systems, Devices, and Methods for Performing a Non-Contact Electrical Measurement on a Cell, Non-Contact Electrical Measurement Cell Vehicle, Chip, Wafer, Die, or Logic Block
Collaborative Learning Model for Semiconductor Applications
System and Method for Product Yield Predication
Patent:
6,449,749 →
Application:
09/442,699 →
System and Method for Storing, Retrieving, and Analyzing Characterization Data
Patent:
6,513,043 →
Application:
09/653,932 →
Method, Apparatus and Product for Evaluating Test Data
Patent:
6,711,514 →
Application:
09/576,330 →
Test Vehicle with Zig-Zag Structures
System and Method for Product Yield Prediction Using Device and Process Neighborhood Characterization Vehicle
Patent:
6,795,952 →
Application:
10/130,448 →
Optimization of Die Placement on Wafers
System and Method for Product Yield Prediction
Efficient Method for Modeling and Simulation of the Impact of Local and Global Variation on Intergrated Circuits
Patent:
6,978,229 →
Application:
09/675,427 →
Zoom in Pin Nest Structure, Test Vehicle Having the Structure, and Method of Fabricating the Structure
Adjusting Die Placement on a Semiconductor Wafer to Increase Yield
Patent:
7,169,638 →
Application:
10/802,549 →
System and Method for Product Yield Prediction
Selecting Die Placement on a Semiconductor Wafer to Reduce Test Time
Patent:
7,190,183 →
Application:
10/799,061 →
Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features
Optimization of Die Placement on Wafers
Patent:
7,334,205 →
Application:
10/995,903 →
Test Structures and Models for Estimating the Yield Impact of Dishing and/or Voids
System and Method for Product Yield Prediction
System and Method for Product Yield Prediction
Back End of Line Clone Test Vehicle
Method and System for Failure Signal Detection Analysis
Method for Improving Mask Layout and Fabrication
Patent:
7,434,197 →
Application:
11/262,148 →
Mapping Yield Information of Semiconductor Dice
Patent:
7,440,869 →
Application:
10/854,970 →
Designing an Integrated Circuit to Improve Yield Using a Variant Design Element
Layout for Dut Arrays Used in Semiconductor Wafer Testing
Identifying Yield-Relevant Process Parameters in Integrated Circuit Device Fabrication Processes
Patent:
7,494,893 →
Application:
11/654,391 →
Fast Localization of Electrical Failures on an Integrated Circuit System and Method
Method for Evaluating the Quality of Data Collection in a Manufacturing Environment
Generalization of the Photo Process Window and Its Application to Opc Test Pattern Design
Apparatus and Method for Electrical Detection and Localization of Shorts in Metal Interconnect Lines
Patent:
7,592,827 →
Application:
11/622,924 →
Method for Reducing Layout Printability Effects on Semiconductor Device Performance
Patent:
7,644,388 →
Application:
11/540,453 →
Inspection Plan Optimization Based on Layout Attributes and Process Variance
Patent:
7,739,065 →
Application:
11/761,455 →
Method for Mapping a Boolean Logic Network to a Limited Set of Application-Domain Specific Logic Cells
Method for the Definition of a Library of Application-Domain-Specific Logic Cells
Test Cells for Semiconductor Yield Improvement
Method and System for Grouping Logic in an Integrated Circuit Design to Minimize Number of Transistors and Number of Unique Geometry Patterns
Patent:
7,827,516 →
Application:
11/969,214 →
Apparatus and Method for Electrical Detection and Localization of Shorts in Metal Interconnect Lines
Patent:
7,888,961 →
Application:
12/564,855 →
Global Predictive Monitoring System for a Manufacturing Facility
High Density Test Structure Array to Support Addressable High Accuracy 4-Terminal Measurements
Patent:
7,902,852 →
Application:
11/827,322 →
Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features
A Measurement Structure in a Standard Cell for Controlling Process Parameters During Manufacturing of an Integrated Circuit
Systems and Methods for Detecting and Monitoring Nickel-Silicide Process and Induced Failures
Patent:
7,932,105 →
Application:
12/251,127 →
Test Structures and Methods for Electrical Characterization of Alignment of Line Patterns Defined with Double Patterning
Patent:
7,935,965 →
Application:
12/152,697 →
Pattern Controlled Ic Layout
Patent:
7,969,199 →
Application:
12/844,568 →
Integrated Circuit Having High Pattern Regularity
Patent:
8,587,341 →
Application:
13/215,834 →
Pprocess for Making and Designing an Ic with Patern Controlled Layout Regions
Patent:
8,004,315 →
Application:
12/853,663 →
Prediction of Impact on Post-Repair Yield Resulting from Manufacturing Process Modification
Patent:
8,037,379 →
Application:
11/469,353 →
Method and Configuration for Connecting Test Structures or Line Arrays for Monitoring Integrated Circuit Manufacturing
Method for the Definition of a Library of Application-Domain-Specific Logic Cells
Reusable Test Chip for Inline Probing of Three Dimensionally Arranged Experiments
Patent:
8,362,480 →
Application:
11/903,943 →
Methods for Yield Variability Benchmarking, Assessment, Quantification, and Localization
Patent:
8,494,817 →
Application:
11/565,573 →
Apparatus and Method for Electrical Detection and Localization of Shorts in Metal Interconnect Lines
Patent:
8,575,955 →
Application:
13/028,138 →
Method for the Definition of a Library of Application-Domain-Specific Logic Cells
High Density Test Structure Array to Support Addressable High Accuracy 4-Terminal Measurements
Patent:
8,901,951 →
Application:
13/022,435 →
Flip-Flop, Latch, and Mux Cells for Use in a Standard Cell Library and Integrated Circuits Made Therefrom
Patent:
9,202,820 →
Application:
14/522,892 →
High-Yielding Standard Cell Library and Circuits Made Therefrom
Patent:
9,438,237 →
Application:
13/866,487 →
Standard Cell Library with Dfm-Optimized M0 Cuts and V0 Adjacencies
Patent:
9,461,065 →
Application:
15/131,020 →
E-Beam Inspection Apparatus and Method of Using the Same on Various Integrated Circuit Chips
Patent:
9,496,119 →
Application:
14/989,743 →
Standard Cell Library with DFM-Optimized M0 Cuts
Patent:
9,529,954 →
Application:
15/067,252 →
Standard Cell Library That Includes 13-Cpp and 17-Cpp D Flip-Flop Cells, with Dfm-Optimized M0 Cuts and V0 Adjacencies
Patent:
9,595,536 →
Application:
15/134,420 →
Integrated Circuit Containing Standard Logic Cells and Library-Compatible, Ncem-Enabled Fill Cells, Including at Least via-Open-Configured, Gate-Short-Configured, Gatecnt-Short- Configured, and Ts-Short-Configured, Ncem-Enabled Fill Cells
Patent:
9,627,370 →
Application:
15/391,001 →
Integrated Circuit Containing Standard Logic Cells and Library-Compatible, NCEM-Enabled Fill Cells, Including at Least Via-Open-Configured, GATE-Short-Configured, GATECNT-Short-Configured, and AA-Short-Configured, NCEM-Enabled Fill Cells
Patent:
9,627,371 →
Application:
15/391,018 →
D Flip-Flop Cells, with DFM-Optimized M0 Cuts and V0 Adjacencies
Patent:
9,627,408 →
Application:
15/259,333 →
Test Structures and Methods for Measuring Silicon Thickness in Fully Depleted Silicon-on-Insulator Technologies
Patent:
9,691,669 →
Application:
14/839,674 →
Ic Chips Containing a Mixture of Standard Cells Obtained from an Original Set of Design Rules and Enhanced Standard Cells That Are a Substantially Uniform Variant of the Original Set of Design Rules and Methods for Making the Same
Patent:
9,704,846 →
Application:
14/991,872 →
E-Beam Inspection Apparatus and Method of Using the Same on Various Integrated Circuit Chips
Integrated Circuit Containing DOEs of NCEM-enabled Fill Cells
Method for Manufacturing a Semiconductor Product Wafer
Patent:
9,847,264 →
Application:
14/946,700 →
Snap-To Valid Pattern System and Method
Patent:
9,870,441 →
Application:
15/073,493 →
Method for Accurate Measurement of Leaky Capacitors Using Charge Based Capacitance Measurements
Patent:
9,952,268 →
Application:
15/269,851 →
Advanced Node Standard Logic Cells that Utilize TS Cut Mask(s) and Avoid DFM Problems Caused by Closely Spaced Gate Contacts and TSCUT Jogs
Patent:
9,984,970 →
Application:
15/712,686 →
Systems, Devices, and Methods for Aligning a Particle Beam and Performing a Non-Contact Electrical Measurement on a Cell and/or Non-Contact Electrical Measurement Cell Vehicle Using a Registration Cell
Related Assignments
(23)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 1, 2014
From: STROJWAS, ANDRZEJ J.; BROZEK, TOMASZ W.; CIPLICKAS, DENNIS J.; KIBARIAN, JOHN K.
To: PDF SOLUTIONS, INC.
Reel/Frame 034288/0404 →
Assignment of Assignor's Interest
Dec 2, 2014
From: CIPLICKAS, DENNIS J.; LAM, STEPHEN; HAIGH, JOHATHAN; ROVNER, VYACHESLAV V.
To: PDF SOLUTIONS, INC.
Reel/Frame 034299/0155 →
Assignment of Assignor's Interest
Feb 4, 2015
From: CIPLICKAS, DENNIS J.; LAM, STEPHEN; HAIGH, JONATHAN; ROVNER, VYACHESLAV V.
To: PDF SOLUTIONS, INC.
Reel/Frame 034884/0558 →
Assignment of Assignor's Interest
Apr 3, 2017
From: DOONG, YIH-YUH; LIN, CHAO-HSIUNG; LIN, SHENG-CHE; KUO, SHIH-PIN
To: PDF SOLUTIONS, INC.
Reel/Frame 041823/0043 →
Assignment of Assignor's Interest
Jun 28, 2017
From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY
To: PDF SOLUTIONS, INC.
Reel/Frame 042848/0029 →
Security Interest
Aug 15, 2017
From: CROWDSTRIKE, INC.
To: SILICON VALLEY BANK
Reel/Frame 043300/0283 →
Assignment of Assignor's Interest
Dec 30, 2017
From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY
To: PDF SOLUTIONS, INC.
Reel/Frame 044509/0403 →
Assignment of Assignor's Interest
Mar 6, 2018
From: DIEHL, DAVID F.; IONESCU, ION-ALEXANDRU; ALPEROVITCH, DMITRI; KURTZ, GEORGE ROBERT
To: CROWDSTRIKE, INC.
Reel/Frame 045122/0138 →
Assignment of Assignor's Interest
Mar 23, 2018
From: TAYCHER, LEONID; COHEN, BENJAMIN; GRUEVSKI, PREDRAG; SHULMAN, MICHAEL
To: KENSHO TECHNOLOGIES INC.
Reel/Frame 045323/0253 →
Assignment of Assignor's Interest
Apr 6, 2018
From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY
To: PDF SOLUTIONS, INC.
Reel/Frame 045467/0534 →
Merger
May 31, 2018
From: AUTUMN MERGER SUB, INC.
To: KENSHO TECHNOLOGIES INC.
Reel/Frame 045948/0246 →
Merger
Jun 8, 2018
From: KENSHO TECHNOLOGIES INC.
To: KENSHO TECHNOLOGIES, LLC
Reel/Frame 046026/0703 →
Assignment of Assignor's Interest
Jul 5, 2018
From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY
To: PDF SOLUTIONS, INC.
Reel/Frame 046267/0422 →
Assignment of Assignor's Interest
Oct 23, 2018
From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY
To: PDF SOLUTIONS, INC.
Reel/Frame 047274/0885 →
Assignment of Assignor's Interest
Mar 12, 2019
From: HAAG, MARION; RINGE, JOCHEN; SITTINGER, MICHAEL; TSCHOPE, CARSTEN
To: CHARITE UNIVERSITATSMEDIZIN BERLIN
Reel/Frame 048568/0686 →
Security Interest
Apr 22, 2019
From: CROWDSTRIKE HOLDINGS, INC.; CROWDSTRIKE, INC.; CROWDSTRIKE SERVICES, INC.
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 048953/0205 →
Patent Security Agreement
Jan 5, 2021
From: CROWDSTRIKE HOLDINGS, INC.; CROWDSTRIKE, INC.
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 054899/0848 →
Assignment of Assignor's Interest
Mar 23, 2023
From: DE, INDRANIL; CHENG, JEREMY; SOKOLLIK, THOMAS; SCHWARZ, YORAM
To: PDF SOLUTIONS, INC.
Reel/Frame 063067/0693 →
Assignment of Assignor's Interest
Aug 15, 2023
From: HONDA, TOMONORI; CHEONG, LIN LEE; BURCH, RICHARD; ZHU, QING
To: PDF SOLUTIONS, INC.
Reel/Frame 064596/0457 →
Assignment of Assignor's Interest
Nov 6, 2023
From: KOSTKA, PETER; SLOMOWITZ, JENNA; MONTGOMERY, DARCY
To: PDF SOLUTIONS, INC.
Reel/Frame 065472/0456 →
Assignment of Assignor's Interest
Jan 6, 2025
From: HONDA, TOMONORI; BURCH, RICHARD; DAVID, JEFFREY DRUE
To: PDF SOLUTIONS, INC.
Reel/Frame 069752/0395 →
Assignment of Assignor's Interest
Feb 4, 2025
From: HONDA, TOMONORI; BURCH, RICHARD; DAVID, JEFFREY DRUE
To: PDF SOLUTIONS, INC.
Reel/Frame 070101/0899 →
Release of Security Interest
Jan 6, 2026
From: FIRST-CITIZENS BANK & TRUST COMPANY
To: CROWDSTRIKE HOLDINGS, INC.; CROWDSTRIKE, INC.
Reel/Frame 074202/0710 →