Direct access memory characterization vehicle

1. A method for designing a test vehicle utilizing a layout of a memory array comprising a plurality of memory bit-cells connected by routing interconnects, a plurality of bit-lines, and a plurality of word-lines, the method comprising:

importing a full-chip layout of the memory array;

partitioning the full-chip layout into a plurality of probe groups, each probe group comprising a plurality of probe pads, and an area of interest (AOI) having at least some of the plurality of memory bit-cells connected by the routing interconnect;

selecting a set of memory bit-cells within the AOI;

removing the previous routing interconnect for the selected set of memory bit-cells;

creating customized interconnect layers (CIL) to reconfigure connection between the selected set of memory bit-cells; and

incorporating the selected set of memory bit-cells with the CIL into the full-chip layout to create a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a memory array with a built-in test vehicle,

wherein the plurality of probe pads comprise bit-line probe pads corresponding to the plurality of bit-lines and word-line probe pads corresponding to the plurality of word-lines, and wherein a number of bit-line probe pads and word-line probe pads that provide a maximum accessible bit count within the memory array is calculated using physical constraints converted to mathematical constraints.

2. The method of claim 1 , wherein the memory array comprises volatile memory array comprising SRAM or DRAM.

3. The method of claim 1 , wherein the memory array comprises a non-volatile memory array comprising one of: NAND Flash, NOR Flash, MRAM, RRAM, PRAM, FeRAM, CeRAM, and X-point.

4. The method of claim 1 , wherein the probe groups are spatially evenly distributed across the layout of the memory array.

5. The method of claim 1 , wherein the bit-lines and the word-lines are substantially perpendicular to each another.

6. The method of claim 1 , wherein at least three probe pads within each probe group are assigned to deep N-well, n-well and ground respectively.

7. The method of claim 1 , wherein the bit-line probe pads are shared within the memory array.

8. The method of claim 7 , wherein the bit-lines conduct current during current-voltage (I-V) measurement.

9. The method of claim 7 , wherein the word-line probe pads are shared across transistor arrays.

10. The method of claim 9 , wherein the word-lines conduct voltage during current-voltage (I-V) measurement.

11. The method of claim 1 , wherein the modified full-chip layout complies with a Design Rule Check (DRC) process.

12. The method of claim 11 , wherein DRC substantially maintains a uniform full chip density across the modified full-chip layout including detecting violations at probe group boundaries.

13. The method of claim 12 , wherein a dummy insertion process is performed before tapeout to comply with manufacturing requirement.

14. The method of claim 1 , wherein the step of selecting the set of memory bit-cells comprises using a pattern extraction method.

15. The method of claim 1 , wherein the step of selecting the set of memory bit-cells comprises using a predefined location within the AOI.

16. The method of claim 15 , wherein the predefined location includes one or more of an edge of a bit-cell, a corner of a bit-cell.

17. A method comprising: importing product mask information for an existing layout design of an integrated circuit chip containing a memory array; and converting the existing layout design of the integrated circuit chip containing the memory array into a modified test chip version of the layout design with a test circuit built into the existing layout design for the integrated circuit chip, including: partitioning the existing layout design into a plurality of probe groups across the integrated circuit chip, wherein each probe group at least comprises (1) a plurality of memory bitcells in an area of interest within the probe group, (2) a plurality of probe pads, and (3) routing interconnecting the plurality of memory bitcells in the area of interest with one or more of the plurality of probe pads; removing routing in the area of interest from the existing layout design of the integrated circuit chip that previously interconnected the plurality of memory bitcells; generating customized interconnect layers to replace the routing of the existing layout design removed from the area of interest, the customized interconnect layers connecting the plurality of memory bitcells with one or more of the plurality of probe pads in the area of interest; and integrating the plurality of memory bitcells and the customized interconnect layers into the existing layout design for the integrated circuit chip to generate the modified version of the layout design comprising a memory array with the built-in test circuit, wherein the plurality of probe pads comprise bit-line probe pads corresponding to a plurality of bit-lines and word-line probe pads corresponding to a plurality of word-lines, and wherein a number of bit-line probe pads and word-line probe pads that provide a maximum accessible bit count within the memory array is calculated using physical constraints converted to mathematical constraints.

18. The method of claim 17 wherein the customized interconnect layers are connected with the plurality of probe pads in the area of interest for current or voltage measurements.

19. The method of claim 17 wherein the customized interconnect layers are connected with the plurality of probe pads in the area of interest for special failure mode characterization.

20. The method of claim 17 wherein the probe groups comprise:

probe pads for bit lines and word lines;

probe pads for the substrate of the integrated circuit; and

vertical and horizontal routing for the plurality of memory bitcells in the area of interest.