IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same

1. An integrated circuit, comprising:

at least a first standard cell logic region and a second standard cell logic region, each of said standard cell logic regions comprised of at least twenty side-by-side abutting standard cells, wherein each standard cell is rectangular in shape, with a height dimension defined by opposing elongated rectangular power and ground rails that extend longitudinally along an entire width dimension of the cell;

the first standard cell logic region further characterized by:

being comprised solely of standard cells of a uniform height H; and,

including at least one cell that implements a first logic function;

the second standard cell logic region further characterized by:

being comprised solely of standard cells of a uniform height H′, where H′ is greater than 1.1×H; and,

including at least one cell that also implements the first logic function;

and wherein:

the at least one cell that implements the first logic function in the first standard cell region has a same width, W, as the at least one cell that implements the first logic function in the second standard cell region; and,

the at least one cell that implements the first logic function in the second standard cell region includes, between its respective power and ground rails, at least two distinct, non-stretched rectangular regions of width W and height greater than zero, and at least one stretched rectangular region of width W and height greater than zero, where a collective height of the non-stretched regions is greater than 0.8× the distance between the nearest edges of the respective power and ground rails in the at least one cell that implements the first logic function in the first standard cell region, and where each of the non-stretched regions consists essentially of patterning identical to that contained in a corresponding region of the at least one cell that implements the first logic function in the first standard cell region.

2. An integrated circuit, as defined in claim 1 , wherein:

the first standard cell logic region further includes at least one cell, of width W′, that implements a second logic function and at least one cell, of width W″, that implements a third logic function; and,

the second standard cell logic region also further includes at least one cell, of width W′, that implements the second logic function and at least one cell, of width W″, that implements the third logic function;

wherein the at least one cell that implements the second logic function in the second standard cell region includes, between its respective power and ground rails, at least two distinct, non-stretched rectangular regions of width W′ and height greater than zero, and at least one stretched rectangular region of width W′ and height greater than zero, where the collective height of the non-stretched regions is greater than 0.8× the distance between the nearest edges of the respective power and ground rails in the at least one cell that implements the second logic function in the first standard cell region, and where each of the non-stretched regions consists essentially of patterning identical to that contained in a corresponding region of the at least one cell that implements the second logic function in the first standard cell region; and,

wherein the at least one cell that implements the third logic function in the second standard cell region includes, between its respective power and ground rails, at least two distinct, non-stretched rectangular regions of width W″ and height greater than zero, and at least one stretched rectangular region of width W″ and height greater than zero, where the collective height of the non-stretched regions is greater than 0.8× the distance between the nearest edges of the respective power and ground rails in the at least one cell that implements the third logic function in the first standard cell region, and where each of the non-stretched regions consists essentially of patterning identical to that contained in a corresponding region of the at least one cell that implements the third logic function in the first standard cell region.

3. The integrated circuit according to claim 1 wherein the uniform height H′ is for an increased height of transistor gates.

4. The integrated circuit according to claim 3 wherein the increased height of transistor gates is proportionally larger for all the cells in the second standard cell region as compared to the cells in the first standard cell region.

5. The integrated circuit according to claim 1 wherein another difference between the first standard cell logic region and the second standard cell logic region includes a lengthening of metal conductor lines.

6. The integrated circuit according to claim 1 wherein another difference between the the first standard cell logic region and the second standard cell logic region includes an increased width of a power rail and a ground rail.

7. The integrated circuit according to claim 1 wherein each of the first and second standard cell regions include cells that implement at least three of: AND, OR, NOT, NAND, NOR, XOR, XNOR, AOI, or OAI logic functions.