Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
View Patent ↗The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
1. A method of making an integrated circuit that includes at least one compiled memory block and multiple logic components having features substantially smaller than wavelength(s) of light used in a lithography process during fabrication of the integrated circuit, the method comprising at least the following:
printing the at least one compiled memory block using lithography settings and optimizations established for bit-cells contained in the compiled memory block;
forming the logic components using regular geometric patterns derived from a regular fabric that controls process variations that impact effective channel length for transistors that define the logic components, said fabric having been designed from the regular geometric patterns that exist in the memory bit-cells; and,
printing the logic components using the lithography settings and optimizations established for the bit-cells.
2. A method of making an integrated circuit, as defined in claim 1 , wherein all geometric shapes in a layer are printed at a fixed pitch, and have a fixed width for the horizontal and vertical directions.
3. A method of making an integrated circuit, as defined in claim 1 , wherein the physical patterns that make up the devices and interconnections in different logic components are consistent with the underlying uniform fabric, and therefore consistent with the illumination setup.
4. A method of making an integrated circuit, as defined in claim 1 , further comprising:
optimizing the uniform patterns of geometrical shapes to match settings for illumination controls that will be used for lithography.
5. A method of making an integrated circuit, as defined in claim 1 , wherein all geometrical shapes of the component features for all devices and interconnections are ultimately derived from combinations of patterns specified by the underlying fabric.
6. A method of making an integrated circuit that includes at least one compiled memory block and multiple logic components having features substantially smaller than wavelength(s) of light used in a lithography process during fabrication of the integrated circuit, the method comprising at least the following:
printing the at least one compiled memory block using component features formed from regular geometric patterns;
printing logic components using component features formed from regular geometric patterns;
wherein the regular geometric patterns that are used to form component features for the memory and the logic have been concurrently designed from a regular fabric that controls process variations that impact effective channel length for transistors that define the logic components.
7. A method of making an integrated circuit, as defined in claim 6 , wherein printing involves utilizing a set of illumination controls compatible with the regular fabric.
8. A method of making an integrated circuit, as defined in claim 6 , wherein all geometrical shapes of the component features for all devices and interconnections are ultimately derived from combinations of patterns specified by the underlying fabric.
9. A method of making an integrated circuit that includes at least one compiled memory block and multiple logic components having features substantially smaller than wavelength(s) of light used in a lithography process during fabrication of the integrated circuit, the method comprising at least the following:
forming the at least one compiled memory block using a set of regular geometric patterns;
forming the logic components using regular geometric patterns derived from a regular fabric that controls process variations that impact effective channel length for transistors that define the logic components, said fabric having been designed from the regular geometric patterns that exist in the memory block; and,
printing the memory block and logic components using the lithography settings established for bit-cells in the compiled memory block.
10. A method of making an integrated circuit, as defined in claim 9 , wherein all geometric shapes in a layer are printed at a fixed pitch, and have a fixed width for the horizontal and vertical directions.
11. A method of making an integrated circuit, as defined in claim 9 , wherein the physical patterns that make up the devices and interconnections in different logic components are consistent with the underlying uniform fabric, and therefore consistent with the illumination setup.
12. A method of making an integrated circuit, as defined in claim 9 , further comprising:
optimizing the uniform patterns of geometrical shapes to match settings for illumination controls that will be used for lithography.
13. A method of making an integrated circuit, as defined in claim 9 , wherein all geometrical shapes of the component features for all devices and interconnections are ultimately derived from combinations of patterns specified by the underlying fabric.