Systems and methods for detecting and monitoring nickel-silicide process and induced failures
View Patent ↗Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.
1. A method of characterizing a Nickel-silicide semiconductor manufacturing process comprising:
accessing a test chip comprising a parallel coupled chain of transistors, wherein said transistors are designed for inducing stress into Nickel-silicide features of said transistors, and for increasing a probability of a manufacturing failure of said Nickel-silicide features;
applying a biasing voltage to one terminal of said parallel coupled chain;
grounding all other terminals of said parallel coupled chain;
measuring current at each of said all other terminals of said parallel coupled chain;
repeating said applying, grounding and measuring for each terminal of said parallel coupled chain;
comparing measured currents from all possible conduction paths to determine a manufacturing defect in said parallel coupled chain of transistors;
changing a process parameter of said Nickel-silicide semiconductor manufacturing process; and
repeating said accessing, said applying, said grounding, said measuring, said repeating said applying, grounding and measuring and said comparing.
2. The method of claim 1 wherein an asymmetry among measured currents indicates a location of said manufacturing defect.
3. The method of claim 1 further comprising comparing failures identified at the previous Nickel-silicide semiconductor manufacturing process to failures identified after said changing said process parameter.
4. A method of changing a Nickel-silicide semiconductor manufacturing process comprising:
accessing a test chip comprising a parallel coupled chain of transistors, wherein said transistors are designed for inducing stress into Nickel-silicide features of said transistors, and for increasing a probability of a manufacturing failure of said Nickel-silicide features;
applying a biasing voltage to one terminal of said parallel coupled chain;
grounding all other terminals of said parallel coupled chain;
measuring current at each of said all other terminals of said parallel coupled chain;
repeating said applying, grounding and measuring for each terminal of said parallel coupled chain;
comparing measured currents from all possible conduction paths to determine a manufacturing defect in said parallel coupled chain of transistors;
changing a process parameter of said Nickel-silicide semiconductor manufacturing process;
second repeating said accessing, applying, grounding, measuring, repeating and comparing; and
second comparing failures identified at first said Nickel-silicide semiconductor manufacturing process to failures identified after said changing.
5. The method of claim 4 further comprising accessing additional test structures on said test chip for monitoring non-defect behavior of said Nickel-silicide semiconductor manufacturing process.
6. The method of claim 5 wherein said additional test structures comprise test structures for measuring sheet resistance of said Nickel-silicide semiconductor manufacturing process.
7. The method of claim 5 wherein said additional test structures comprise test structures for identifying polysilicon shadowing effects of said Nickel-silicide semiconductor manufacturing process.
8. The method of claim 5 wherein said additional test structures comprise test structures for increasing stress by reducing transistor width below process design rule minimums.