Process for making and designing an IC with pattern controlled layout regions
View Patent ↗The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.
1. A method for making an integrated circuit having geometric features corresponding to at least active, poly, contact, m1, m2 and via layer patterning, said method comprising at least:
providing a silicon wafer to a fabrication line capable of rendering geometric features in said wafer at a resolution of 28 nm or less;
fabricating, using said fabrication line, the geometric features corresponding to said active, poly, contact, m1, m2 and via layer patterning;
wherein said fabricating includes creating, within a continuous region of at least 100×100 um 2 , geometric features in the active, poly, m1, and m2 layers exclusively from patterning having been defined by:
instantiating at least 100 abutting instances of a predefined base template at a spacing corresponding to a minimum poly-to-poly pitch for the fabrication line, wherein said base template defines patterning corresponding to the active, poly, contact, m1, m2 and via layers of said integrated circuit;
instantiating one or more regular connector templates within a majority of the instantiated base templates, each regular connector template selected from a set of fewer than 20 types of regular connector templates, wherein each type of regular connector template defines patterning corresponding to the active, poly, contact, m1, m2 or via layer of said integrated circuit, and wherein each type of regular connector template is eligible for instantiation at between one and 5 locations relative to a reference location in its associated base template; and,
instantiating one or more special connector templates within fewer than 5 percent of the instantiated base templates, each special connector template selected from a set of fewer than 3 types of special connector templates, wherein each type of special connector template defines patterning corresponding to the contact, m1, m2 or via layer of said integrated circuit, and wherein each type of special connector template is eligible for instantiation at a single location relative to a reference location in its associated base template.
2. The method of claim 1 , wherein the fabricated continuous region is at least 250×250 um 2 in size.
3. The method of claim 1 , wherein the fabricated continuous region is at least 500×500 um 2 in size.
4. The method of claim 1 , wherein the set of regular connector templates comprises fewer than ten types of regular connector templates.
5. The method of claim 1 , wherein the set of regular connector templates comprises fewer than five types of regular connector templates.
6. The method of claim 1 , wherein the instantiating of special connector templates occurs within few than one percent of the instantiated base templates.
7. The method of claim 1 , wherein each regular connector template type is pre-qualified for instantiation at each eligible location regardless of which other regular connector templates are instantiated at neighboring locations.
8. The method of claim 1 , wherein each regular connector template type is selected for pattern compatibility with the associated base template.
9. An integrated circuit having geometric features corresponding to at least active, poly, contact, m1, m2 and via layer patterning, said integrated circuit made by a method comprising at least the following steps:
providing a silicon wafer to a fabrication line capable of rendering geometric features in said wafer at a resolution of 65 nm or less;
fabricating, using said fabrication line, the geometric features corresponding to said active, poly, contact, m1, m2 and via layer patterning;
wherein said fabricating includes creating, within a continuous region of at least 500×500 um 2 , geometric features in the active, poly, m1, and m2 layers exclusively from patterning having been defined by:
instantiating at least 100 abutting instances of a predefined base template at a minimum poly-to-poly pitch for the fabrication line, wherein said base template defines patterning corresponding to the active, poly, contact, m1, m2 and via layers of said integrated circuit;
instantiating one or more regular connector templates within a majority of the instantiated base templates, each regular connector template selected from a set of fewer than ten types of regular connector templates, wherein each type of regular connector template defines patterning corresponding to the active, poly, contact, m1, m2 or via layer of said integrated circuit, and wherein each type of regular connector template is eligible for instantiation at between one and five locations relative to a reference location in its associated base template; and,
instantiating one or more special connector templates within fewer than ten percent of the instantiated base templates, each special connector template selected from a set of fewer than four types of special connector templates, wherein each type of special connector template defines patterning corresponding to the contact, m1, m2 or via layer of said integrated circuit, and wherein each type of special connector template is eligible for instantiation at a single location relative to a reference location in its associated base template.
10. The method of claim 9 , wherein the set of regular connector templates comprises fewer than five types of regular connector templates.
11. The method of claim 9 , wherein the instantiating of special connector templates occurs within few than five percent of the instantiated base templates.
12. The method of claim 9 , wherein each regular connector template type is pre-qualified for instantiation at each eligible location regardless of which other regular connector templates are instantiated at neighboring locations.
13. The method of claim 9 , wherein each regular connector template type is selected for pattern compatibility with the associated base template.
14. The method of claim 9 , wherein said continuous region realizes a template regularity metric of at least 50% for the m1 and m2 layers.
15. A method for designing an integrated circuit having geometric features corresponding to at least active, poly, contact, m1, m2 and via layer patterning, said method comprising at least the following:
defining a continuous region of at least 20×20 um 2 containing geometric features in the active, poly, m1, and m2 layers of said integrated circuit exclusively from patterning having been determined by:
instantiating at least 100 abutting instances of a predefined base template at a minimum poly-to-poly pitch, wherein said base template defines patterning corresponding to the active, poly, contact, m1, m2 and via layers of said integrated circuit;
instantiating one or more regular connector templates within a majority of the instantiated base templates, each regular connector template selected from a set of fewer than 20 types of regular connector templates, wherein each type of regular connector template defines patterning corresponding to the active, poly, contact, m1, m2 or via layer of said integrated circuit, and wherein each type of regular connector template is eligible for instantiation at between one and 5 locations relative to a reference location in its associated base template; and,
instantiating one or more special connector templates within fewer than 10% of the instantiated base templates, each special connector template selected from a set of fewer than 4 types of special connector templates, wherein each type of special connector template defines patterning corresponding to the contact, m1, m2 or via layer of said integrated circuit, and wherein each type of special connector template is eligible for instantiation at a single location relative to a reference location in its associated base template.
16. The method of claim 15 , wherein the continuous region is at least 250×250 um 2 in size.
17. The method of claim 15 , wherein the continuous region is at least 500×500 um 2 in size.
18. The method of claim 15 , wherein the instantiating of special connector templates occurs within few than one percent of the instantiated base templates.
19. The method of claim 15 , wherein each regular connector template type is pre-qualified for instantiation at each eligible location regardless of which other regular connector templates are instantiated at neighboring locations.
20. The method of claim 15 , wherein each regular connector template type is selected for pattern compatibility with the associated base template.