IC with test structures and e-beam pads embedded within a contiguous standard cell area

1. An integrated circuit (IC) that includes a plurality of patterned layers, including at least a first conductive layer, a second conductive layer, and a gate layer, wherein said patterned layers form a contiguous standard cell area that comprises a mix of at least one thousand logic cells and fill cells, placed into at least twenty vertically adjacent rows, with at least twenty cells placed horizontally side-by-side in each row, wherein each cell comprises:

elongated upper and lower supply rails, each formed in the first conductive layer, each extending longitudinally in the horizontal direction across the cell to abut with corresponding upper/lower supply rails in adjacent cells;

a plurality of elongated gate stripes, each extending longitudinally in the vertical direction between corresponding upper and lower supply rails, the elongated gate stripes evenly spaced at a uniform gate-to-gate pitch in the horizontal direction;

1 st , 2 nd , 3 rd , 4 th and 5 th first-layer conductive tracks, each extending longitudinally in the horizontal direction, each of said first-layer conductive tracks vertically positioned between the upper and lower supply rails and evenly spaced in the vertical direction, each of said first-layer conductive tracks defining an area where patterning in the first conductive layer may appear; and,

at least 1 st , 2 nd and 3 rd second-layer conductive tracks, each extending longitudinally in the vertical direction, each of said second-layer conductive tracks positioned between adjacent elongated gate stripes and evenly spaced in the horizontal direction at the uniform gate-to-gate pitch, each of said second-layer conductive tracks defining an area where patterning in the second conductive layer may appear;

wherein the improvement comprises:

first, second, and third 4×3 e-beam pads, each contained within the contiguous standard cell area, wherein each of the 4×3 e-beam pads comprises:

four elongated first-layer features, each at least three times the uniform gate-to-gate pitch in length, said four first-layer features patterned in four vertically adjacent first-layer conductive tracks;

three elongated second-layer features, patterned in three adjacent second-layer conductive tracks;

wherein the four first-layer features and three second-layer features are arranged so as to overlap at twelve overlap points, with three overlap points in each of the adjacent first-layer conductive tracks; and,

six contacts/vias, each placed at an overlap point, and configured to electrically connect all of the first-layer and second-layer features together; and,

first, second, and third test area geometries, the first test area geometry electrically connected between the first 4×3 e-beam pad and an upper or lower supply rail, the second test area geometry electrically connected between the second 4×3 e-beam pad and an upper or lower supply rail, and the third test area geometry electrically connected between the third 4×3 e-beam pad and an upper or lower supply rail;

wherein:

the first test area geometry comprises tip-to-tip short or leakage test area geometry;

the second test area geometry comprises tip-to-side short or leakage test area geometry; and,

the third test area geometry comprises via-chamfer short or leakage test area geometry.

2. An IC, as defined in claim 1 , wherein within the contiguous standard cell area, the supply rails and 2 nd and 4 th first-layer conductive tracks are patterned with a first mask exposure and the 1 st , 3 rd and 5 th first-layer conductive tracks are patterned with a second mask exposure.

3. An IC, as defined in claim 1 , wherein within the contiguous standard cell area, the 1 st , 3 rd and 5th first-layer conductive tracks are patterned with a first mask exposure and the supply rails and 2 nd and 4 th first-layer conductive tracks are patterned with a second mask exposure.

4. An IC, as defined in claim 1 , wherein said IC also includes a source/drain (AA) layer and a source/drain silicide (TS) layer, and the second conductive layer is the TS layer.

5. An IC, as defined in claim 4 , wherein the first conductive layer is located above the gate layer and above the TS layer.

6. An IC, as defined in claim 5 , wherein the first test area geometry and the first 4×3 e-beam pad are both instantiated at the same fill cell position within the contiguous standard cell area.

7. An IC, as defined in claim 6 , wherein the second test area geometry and the second 4×3 e-beam pad are both instantiated at the same fill cell position within the contiguous standard cell area.

8. An IC, as defined in claim 7 , wherein the third test area geometry and the third 4×3 e-beam pad are both instantiated at the same fill cell position within the contiguous standard cell area.

9. An IC, as defined in claim 1 , wherein within each 4×3 e-beam pad, no two vertically adjacent first-layer conductive tracks contain any horizontally aligned contacts/vias.

10. An IC, as defined in claim 1 , wherein within each 4×3 e-beam pad, the uppermost and lowermost first-layer conductive tracks each contain two contacts/vias, whereas the middle two first-layer conductive tracks each contain only a single contact/via.

11. An IC, as defined in claim 1 , wherein the contiguous standard cell area includes at least ten instances of 4×3 e-beam pads and at least ten instances of associated test area geometry.

12. An IC, as defined in claim 11 , wherein the contiguous standard cell area includes at least one-hundred instances of 4×3 e-beam pads and at least one-hundred instances of associated test area geometry.

13. An IC, as defined in claim 12 , wherein the contiguous standard cell area includes at least five-hundred instances of 4×3 e-beam pads and at least five-hundred instances of associated test area geometry.

14. An IC, as defined in claim 4 , wherein the contiguous standard cell area further includes additional test area geometry selected from a list that consists of:

tip-to-tip-short-configured test area geometry;

tip-to-tip-leakage-configured test area geometry;

tip-to-side-short-configured test area geometry;

tip-to-side-leakage-configured test area geometry;

side-to-side-short-configured test area geometry;

side-to-side-leakage-configured test area geometry;

L-shape-interlayer-short-configured test area geometry;

L-shape-interlayer-leakage-configured test area geometry;

diagonal-short-configured test area geometry;

diagonal-leakage-configured test area geometry;

corner-short-configured test area geometry;

corner-leakage-configured test area geometry;

interlayer-overlap-short-configured test area geometry;

interlayer-overlap-leakage-configured test area geometry;

via-chamfer-short-configured test area geometry;

via-chamfer-leakage-configured test area geometry;

merged-via-short-configured test area geometry;

merged-via-leakage-configured test area geometry;

snake-open-configured test area geometry;

snake-resistance-configured test area geometry;

stitch-open-configured test area geometry;

stitch-resistance-configured test area geometry;

via-open-configured test area geometry;

via-resistance-configured test area geometry;

metal-island-open-configured test area geometry;

metal-island-resistance-configured test area geometry;

merged-via-open-configured test area geometry; and,

merged-via-resistance-configured test area geometry.