On-chip capacitance measurement for memory characterization vehicle
View Patent ↗A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.
1. A method for designing a parametric test vehicle for bit-line capacitance measurement utilizing a layout of a memory chip comprising a plurality of bit-lines addressing a plurality of memory bit-cells in a memory block, the method comprising:
importing a layout of the memory chip;
selecting a first pair of transistors, comprising a first PMOS transistor and a first NMOS transistor, from the layout of the memory chip;
removing existing routing interconnect for the selected first PMOS transistor and the first NMOS transistor;
creating customized interconnect layers (CIL) to connect the first PMOS transistor to one end of a bit-line at one side of the memory block, and, to connect the first NMOS transistor to the same end or a different end of the same bit-line;
driving the PMOS transistor with a first clock signal, and driving the NMOS transistor with a second clock signal, wherein the first clock signal and the second clock signal are synchronized but non-overlapping;
measuring current flowing through the bit-line to calculate a capacitance of the bit-line; and
incorporating the selected PMOS and NMOS transistors with the CIL into the layout of the memory chip to create a modified memory chip layout, such that a wafer fabricated using the modified memory chip layout comprises a memory chip with a built-in test vehicle for capacitance measurement.
2. The method of claim 1 , wherein the first PMOS and the first NMOS transistors are connected at the same end of a bit-line on the same side of the memory block.
3. The method of claim 1 , wherein the first PMOS and the first NMOS transistors are connected at different ends of a bit-line on opposite sides of the memory block.
4. The method of claim 1 , wherein the memory array comprises volatile memory array comprising SRAM or DRAM.
5. The method of claim 1 , wherein the memory array comprises a non-volatile memory array comprising one of: NAND Flash, NOR Flash, MRAM, RRAM, PRAM, FeRAM, CeRAM, and X-point.
6. The method of claim 1 , wherein the memory chip further comprises a plurality of word-lines addressing the plurality of memory bit-cells in the memory block, and wherein the method further comprises:
selecting a second pair of transistors, comprising a second PMOS transistor and a second NMOS transistor, from the layout of the memory chip;
removing existing routing interconnect for the selected second PMOS transistor and the second NMOS transistor;
creating routing paths within the CIL to connect the second PMOS transistor to one end of a word-line at a side of the memory block, and, to connect the second NMOS transistor to the same end or a different end of the same word-line;
driving the second PMOS transistor with a third clock signal, and driving the second NMOS transistor with a fourth clock signal, wherein the third clock signal and the fourth clock signal are synchronized but non-overlapping;
measuring current flowing through the word-line to calculate a capacitance of the word-line; and
incorporating the selected second PMOS and second NMOS transistors with the routing paths within the CIL into the modified layout of the memory chip, so that the built-in test vehicle can measure both bit-line and word-line capacitance.
7. The method of claim 6 , wherein the third clock signal and the fourth clock signals are identical to the first clock signal and the second clock signal respectively.
8. The method of claim 6 , wherein a capacitance of a memory bit-cell is calculated by changing word-line state without having to independently measure bit-cell capacitance.
9. The method of claim 6 , wherein the bit-lines and the word-lines are substantially perpendicular to one another.
10. The method of claim 1 , wherein the first PMOS transistor and the first NMOS transistor are selected from on-chip circuitry for the memory block.
11. The method of claim 10 , wherein the on-chip circuitry is for one of: word-line driver, bit-line pre-amplifier, row/column decoder.
12. A method for designing a parametric test vehicle for word-line capacitance measurement utilizing a layout of a memory chip comprising a plurality of word-lines addressing a plurality of memory bit-cells in a memory block, the method comprising:
importing a layout of the memory chip;
selecting a first pair of transistors, comprising a first PMOS transistor and a first NMOS transistor, from the layout of the memory chip;
removing existing routing interconnect for the selected first PMOS transistor and the first NMOS transistor;
creating customized interconnect layers (CIL) to connect the first PMOS transistor to one end of a word-line at one side of the memory block, and, to connect the first NMOS transistor to the same end or a different end of the same word-line;
driving the PMOS transistor with a first clock signal, and driving the NMOS transistor with a second clock signal, wherein the first clock signal and the second clock signal are synchronized but non-overlapping;
measuring current flowing through the word-line to calculate a capacitance of the word-line; and
incorporating the selected PMOS and NMOS transistors with the CIL into the layout of the memory chip to create a modified memory chip layout, such that a wafer fabricated using the modified memory chip layout comprises a memory chip with a built-in test vehicle for capacitance measurement.
13. The method of claim 12 , wherein the first PMOS and the first NMOS transistors are connected at the same end of a bit-line on the same side of the memory block.
14. The method of claim 12 , wherein the first PMOS and the first NMOS transistors are connected at different ends of a bit-line on opposite sides of the memory block.
15. The method of claim 12 , wherein the memory array comprises volatile memory array comprising SRAM or DRAM.
16. The method of claim 12 , wherein the memory array comprises a non-volatile memory array comprising one of: NAND Flash, NOR Flash, MRAM, RRAM, PRAM, FeRAM, CeRAM, and X-point.
17. The method of claim 12 , wherein the memory chip further comprises a plurality of bit-lines addressing the plurality of memory bit-cells in the memory block, and wherein the method further comprises:
selecting a second pair of transistors, comprising a second PMOS transistor and a second NMOS transistor, from the layout of the memory chip;
removing existing routing interconnect for the selected second PMOS transistor and the second NMOS transistor;
creating routing paths within the CIL to connect the second PMOS transistor to one end of a bit-line at a side of the memory block, and, to connect the second NMOS transistor to the same end or a different end of the same bit-line;
driving the second PMOS transistor with a third clock signal, and driving the second NMOS transistor with a fourth clock signal, wherein the third clock signal and the fourth clock signal are synchronized but non-overlapping;
measuring current flowing through the word-line to calculate a capacitance of the bit-line; and
incorporating the selected second PMOS and second NMOS transistors with the routing paths within the CIL into the modified layout of the memory chip, so that the built-in test vehicle can measure both bit-line and word-line capacitance.
18. The method of claim 17 , wherein the third clock signal and the fourth clock signals are identical to the first clock signal and the second clock signal respectively.
19. The method of claim 17 , wherein a capacitance of a memory bit-cell is calculated by changing word-line state without having to independently measure bit-cell capacitance.
20. The method of claim 17 , wherein the bit-lines and the word-lines are substantially perpendicular to one another.
21. The method of claim 12 , wherein the first PMOS transistor and the first NMOS transistor are selected from on-chip circuitry for the memory block.
22. The method of claim 21 , wherein the on-chip circuitry is for one of: word-line driver, bit-line pre-amplifier, row/column decoder.