Method for accurate measurement of leaky capacitors using charge based capacitance measurements
Disclosed are methods for measuring capacitance in presence of leakage in integrated circuits. In particular, it teaches a method of measuring leaky capacitors using charge based capacitance measurement (CBCM) technique taking into account parasitic resistance. Fast and accurate measurement of capacitances allows the estimation of a number of technology parameters like: gate-dielectric thickness, gate critical dimension, trench depth in a damascene metallization process, height of a fin in a Fin FET device etc.
1. A method of monitoring performance of an integrated circuit device using a charge based capacitance measurement (CBCM) technique, the method comprising:
providing a metrology structure having a leaky capacitor in a wafer that is disposed adjacent another wafer containing or contains the integrated circuit device, and a pseudo-inverter capable of pulling-up a voltage V;
charging and discharging the leaky capacitor in the wafer that is disposed adjacent the another wafer containing or contains the integrated circuit device by the pseudo-inverter, the pseudo-inverter having a time period P and a pulse width T during which the leaky capacitor is charged;
measuring a current at the pull-up voltage V;
estimating a value of capacitance of the leaky capacitor based on the measured current;
plotting the estimated value of the capacitance of the leaky capacitor in the wafer that is disposed adjacent the another wafer containing or contains the integrated circuit device versus T to obtain a value of a slope that is indicative of leakage in the leaky capacitor in the wafer that is disposed adjacent the another wafer containing or contains the integrated circuit device; and
using the value of the slope to extract a dimension of a structure in the integrated circuit device, wherein the dimension is associated with the leaky capacitor in the wafer that is disposed adjacent the another wafer containing or contains the integrated circuit device, where an accuracy of the dimension of the structure associated with the leaky capacitor is directly related to an accurate monitoring of the performance of the integrated circuit device.
2. The method of claim 1 , wherein the metrology structure further comprises a resistor in parallel with the leaky capacitor that is also disposed in the wafer that is disposed adjacent the another wafer containing or contains the integrated circuit device, and the slope is calculated for different values of the resistor.
3. The method of claim 2 , wherein estimating the value of the capacitance includes using the following equation:
C
meas
=
I
Vf
=
C
+
T
R
2
where C meas is the measured value of the capacitance; I is the measured current for the time period P with pulse width T; V is the voltage applied to the pseudo-inverter; f is the frequency of the pulse; C is the true value of the capacitance, and R 2 is the value of the resistor.
4. The method of claim 1 , wherein the pseudo-inverter constitutes a switch comprising a pull-up transistor and a pull-down transistor.
5. The method of claim 1 , wherein the CBCM technique comprises a charge-injection-error-free (CIEF) CBCM technique.
6. The method of claim 1 , wherein the metrology structure is disposed on the wafer that contains the integrated circuit device to be fabricated.
7. The method of claim 1 , wherein the metrology structure is disposed on the wafer that is adjacent to the another wafer that contains the integrated circuit device during fabrication.
8. The method of claim 1 , wherein the leaky capacitor is part of the front-end-of-the-line (FEOL) capacitors in the integrated circuit.
9. The method of claim 1 , wherein the dimension extracted from the value of the slope comprises thickness of a gate dielectric in the integrated circuit.
10. The method of claim 1 , wherein the dimension extracted from the value of the slope comprises height of a fin in a FinFET device.
11. The method of claim 1 , wherein the dimension extracted from the value of the slope comprises critical dimension of a gate.
12. The method of claim 1 , wherein the dimension extracted from the value of the slope comprises trench depth in a damascene metallization process.
13. The method of claim 1 , wherein the metrology structure includes a parasitic series resistance.
14. The method of claim 3 , wherein the metrology structure is disposed on the wafer that has the integrated circuit device to be fabricated.
15. The method of claim 3 , wherein during fabrication the metrology structure is disposed on the wafer that is adjacent to the wafer having the integrated circuit device.