Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs
View Patent ↗An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent shorts/leakages that can degrade manufacturing yield or performance.
1. A process for making an integrated circuit (IC) through use of at least an n-well (NW) mask, a source/drain (RX) mask, a gate (PC) mask, a gate cut (CT) mask, a source/drain silicide (TS) mask, a silicide cut (TSCUT) mask, a source/drain contact (CA) mask, a gate contact (GO) mask, a local interconnect (M0) mask, an M0 cut (M0CUT) mask, a first interconnect via (V0) mask, and a first interconnect layer (M1) mask, said process including:
instantiating at least 1000 standard logic cells, implementing at least 20 distinct logical functions, by, for each of said cells:
patterning identically spaced power rails that extend longitudinally in a first direction;
patterning identically spaced gate stripes that extend longitudinally in a second direction, perpendicular to the first direction, with adjacent gate stripes having a center-to-center perpendicular spacing of CPP;
patterning four or fewer M0 wiring tracks, extending longitudinally in the first direction, between each pair of adjacent power rails; and,
patterning additional features using one or more NW, RX, CT, TS, TSCUT, CA, GO, and M0CUT masks;
such that each of said standard logic cells is configured to permit abutted instantiation with others of said standard logic cells;
each of said standard logic cells further characterized in that:
for any and all gate contact(s) formed by a GO mask feature that partially overlaps a TSCUT mask, the distance from the center point of said GO mask feature to the nearest jog in the TSCUT mask is at least 0.5×CPP.
2. A process, as defined in claim 1 , wherein each of said standard logic cells is further characterized in that
for any and all gate contact(s) formed by a GO mask feature that partially overlaps a TSCUT mask, the distance from the center point of said GO mask feature to the nearest jog in the TSCUT mask is at least 0.8×CPP.
3. A process, as defined in claim 2 , wherein each of said standard logic cells is further characterized in that
for any and all gate contact(s) formed by a GO mask feature that partially overlaps a TSCUT mask, the distance from the center point of said GO mask feature to the nearest jog in the TSCUT mask is at least CPP.
4. A process, as defined in claim 1 , wherein the process produces an IC in the form of a silicon wafer.
5. A process, as defined in claim 1 , wherein the process produces an IC in the form of an unpackaged silicon die.
6. A process, as defined in claim 1 , wherein the process produces an IC in the form of a packaged chip.