Snap-to valid pattern system and method
Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.
1. A method of creating a snap-to instruction for forming at least one physical pattern on one of a plurality of layers in a semiconductor integrated circuit, the method comprising the steps of:
determining a plurality of golden cell valid patterns, the plurality of golden cell valid patterns defined by data and wherein the plurality of golden cell valid patterns contain every allowable pattern; and
creating a snap-to instruction that automatically alters an invalid pattern defined by other data into a valid pattern based upon at least one of the plurality of golden cell valid patterns, the snap-to instruction determining a valid size and a valid position that approximates an invalid size and an invalid position of the invalid pattern, wherein the valid pattern includes at least a valid size and a valid position, the snap-to instruction including a snap-to valid via pattern instruction that provides for a valid extension of a valid via pattern, wherein the valid extension includes a valid distance of an enclosing shape that surrounds a via pattern.
2. The method according to claim 1 further including a snap-to route instruction that provides for a valid route, wherein the valid route includes a valid width and a valid long axis position.
3. The method according to claim 1 further including a snap-to valid line end instruction that provides for a valid line end, wherein the valid line end includes a valid width and a valid short end position.
4. The method according to claim 1 further including a snap-to valid size instruction that provides for a valid size, wherein the valid size includes a valid height and a valid width.
5. The method according to claim 1 further including a snap-to valid position instruction that provides for a valid position, wherein the valid position includes a valid size and a valid X,Y position.
6. The method according to claim 1 , further including a snap-to valid enclosure instruction that provides for a valid enclosure corresponding to the enclosing shape, wherein the valid enclosure includes three shortest distances from the valid via pattern to the enclosing shape.
7. The method according to claim 1 , wherein determining a plurality of golden cell valid patterns includes determining a specification of one or more types of patterns of interest, the one or more types of patterns comprising a subset of the plurality of golden cell valid patterns.
8. The method according to claim 1 , wherein extension and/or enclosure patterns are distinguished by the x,y position of the center of the shape, and wherein position patterns can be coupled with size patterns thereby fully characterizing a rectangle of a given layer.
9. The method of claim 1 further comprising the step of, subsequent to determining a plurality of golden cell valid patterns, filtering out one or more undesired valid patterns among the plurality of golden cell valid patterns.
10. The method of claim 1 , wherein the valid pattern is chosen from amongst a plurality of valid patterns based on selecting a target pattern among the plurality of valid patterns having a minimum difference between the invalid pattern and the valid pattern.