Integrated circuit having high pattern regularity
View Patent ↗The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.
1. A portion of an integrated circuit having geometric features defined at a resolution of 28 nm or less, said features corresponding to at least active, poly, first metal, and second metal layers, said integrated circuit portion comprising at least:
a continuous region of at least 100×100 um 2 tiled with abutting baseTemplate frames, each baseTemplate frame defined on either side by adjacent, minimum-spaced poly tracks and on top and bottom by opposing positive and negative supply rails in the first or second metal layer;
each of said baseTemplate frames containing at least some geometric features in each of the active, poly, first metal, and second metal layers;
said continuous region characterized in that:
(i) the poly layer features within said continuous region exhibit a template regularity metric of greater than 90%;
(ii) the first metal layer features within said continuous region exhibit a template regularity metric of greater than 50%; and,
(iii) the second metal layer features within said continuous region exhibit a template regularity metric of greater than 50%;
said continuous region also including:
(a) at least two distinct types of special connectors, each instantiated within fewer than 5% of said baseTemplate frames, each of said special connector types comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame; and,
(v) cells implementing at least six distinct logic functions.
2. The integrated circuit portion of claim 1 , wherein said continuous region is at least 250×250 um 2 in size.
3. The integrated circuit portion of claim 1 , wherein said continuous region is at least 500×500 um 2 in size.
4. The integrated circuit portion of claim 1 , further including at least one additional type of special connector, instantiated within fewer than 5% of said baseTemplate frames, said additional special connector type comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame.
5. The integrated circuit portion of claim 1 , further including at least two additional types of special connectors, each instantiated within fewer than 5% of said baseTemplate frames, each of said two additional special connector types comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame.
6. The integrated circuit portion of claim 1 , wherein the cells implementing at least six distinct logic functions include at least inverter, nor2, and nand2.
7. The integrated circuit portion of claim 1 , wherein the cells implementing at least six distinct logic functions further include at least aoi221 and flip-flop with scan and reset.
8. A portion of an integrated circuit having geometric features defined at a resolution of 28 nm or less, said features corresponding to at least active, poly, first metal, and second metal layers, said integrated circuit portion comprising at least:
a continuous region of at least 20×20 um 2 tiled with abutting baseTemplate frames, each baseTemplate frame defined on either side by adjacent, minimum-spaced poly tracks and on top and bottom by opposing positive and negative supply rails in the first or second metal layer;
each of said baseTemplate frames containing at least some geometric features in each of the active, poly, first metal, and second metal layers;
said continuous region characterized in that:
(i) the poly layer features within said continuous region exhibit a template regularity metric of greater than 90%;
(ii) the first metal layer features within said continuous region exhibit a template regularity metric of greater than 60%; and,
(iii) the second metal layer features within said continuous region exhibit a template regularity metric of greater than 60%;
said continuous region also including:
(a) at least three distinct types of special connectors, each instantiated within fewer than 10% of said baseTemplate frames, each of said special connector types comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame; and,
(v) cells implementing at least five distinct logic functions, including at least one or 22ao22nand2 cell.
9. The integrated circuit portion of claim 8 , wherein said continuous region is at least 100×100 um 2 in size.
10. The integrated circuit portion of claim 8 , wherein said continuous region is at least 250×250 um 2 in size.
11. The integrated circuit portion of claim 8 , wherein the cells implementing at least five distinct logic functions further include at least inverter, nor2, and nand2.
12. The integrated circuit portion of claim 11 , wherein the cells implementing at least five distinct logic functions further include at least aoi221.
13. A portion of an integrated circuit having geometric features defined at a resolution of 28 nm or less, said features corresponding to at least active, poly, first metal, and second metal layers, said integrated circuit portion comprising at least:
a continuous region of at least 100×100 um 2 tiled with abutting baseTemplate frames, each baseTemplate frame defined on either side by adjacent, minimum-spaced poly tracks and on top and bottom by opposing positive and negative supply rails in the first or second metal layer;
each of said baseTemplate frames containing at least some geometric features in each of the active, poly, first metal, and second metal layers;
said continuous region characterized in that:
(i) the poly layer features within said continuous region exhibit a template regularity metric of greater than 90%;
(ii) the first metal layer features within said continuous region exhibit a template regularity metric of at least 64%; and,
(iii) the second metal layer features within said continuous region exhibit a template regularity metric of greater than 50%;
said continuous region also including:
(a) at least two distinct types of special connectors, each instantiated within fewer than 10% of said baseTemplate frames, each of said special connector types comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame; and,
(v) cells implementing at least six distinct logic functions.
14. The integrated circuit portion of claim 13 , wherein said continuous region is at least 250×250 um 2 in size.
15. The integrated circuit portion of claim 13 , wherein said continuous region is at least 500×500 um 2 in size.
16. The integrated circuit portion of claim 13 , further including at least one additional type of special connector, instantiated within fewer than 10% of said baseTemplate frames, said additional special connector type comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame.
17. The integrated circuit portion of claim 13 , further including at least two additional types of special connectors, each instantiated within fewer than 10% of said baseTemplate frames, each of said two additional special connector types comprising predetermined patterning in the first or second metal layer located at a fixed location relative to a reference location in its associated baseTemplate frame.
18. The integrated circuit portion of claim 13 , wherein the cells implementing at least six distinct logic functions include at least inverter, nor2, and nand2.
19. The integrated circuit portion of claim 18 , wherein the cells implementing at least six distinct logic functions further include at least aoi221.
20. The integrated circuit portion of claim 13 , wherein the first metal layer comprises a contact layer used for local interconnections.