Measurement structure in a standard cell for controlling process parameters during manufacturing of an integrated circuit

1. An apparatus for use in an integrated circuit, comprising:

a standard cell, wherein the standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit,

wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit,

wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell,

wherein the measuring structure includes at least one feature in at least one of the plurality of material layers and the plurality of mask layers,

wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

2. The apparatus of claim 1 , wherein the measuring structure comprises at least one feature of a critical dimension feature, a dense feature, an isolated feature, an overlay feature and a subresolution assist feature.

3. The apparatus of claim 1 , wherein the standard cell is a filler cell.

4. The apparatus of claim 1 , wherein the standard cell comprises a plurality of measuring structures and the plurality of measuring structures is placed in a plurality of layers of the standard cell.

5. The apparatus of claim 1 , wherein a metal layer of the standard cell comprises a voltage rail.

6. A standard cell library, comprising:

a standard cell, wherein the standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit,

wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit,

wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell,

wherein the measuring structure includes at least one feature that is included in at least one of the plurality of material layers and the plurality of mask layers,

wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

7. The standard cell library of claim 6 , wherein the measuring structure comprises at least one feature of a critical dimension feature, a dense feature, an isolated feature, an overlay feature and a subresolution assist feature.

8. The standard cell library of claim 6 , wherein the standard cell is a filler cell, and further comprising a functional cell, wherein a height of the functional cell and a height of the filler cell is substantially the same.

9. The standard cell library of claim 8 , wherein the filler cell and the functional cell comprise a voltage rail in the same metal layer.

10. An integrated circuit, comprising:

a standard cell, wherein the standard cell is formed in a plurality of material layers of the integrated circuit to perform part of a function of the integrated circuit,

wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit,

wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell,

wherein the measuring structure includes at least one feature that is included in at least one of the plurality of material layers and the plurality of mask layers,

wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

11. The integrated circuit of claim 10 , wherein the measuring structure comprises at least one feature of a critical dimension feature, a dense feature, an isolated feature, an overlay feature and a subresolution assist feature.

12. The integrated circuit of claim 10 , wherein the standard cell is a filler cell, and further comprising functional cells, wherein the filler cell is arranged between functional cells.

13. The integrated circuit of claim 12 , wherein the measuring structure of the filler cell is electrically isolated from the functional cells.

14. The integrated circuit of claim 12 , wherein the filler cell is configured to fill a space between a first functional cell and a second functional cell and to route a voltage from the first functional cell to the second functional cell.

15. The integrated circuit of claim 12 , wherein the integrated circuit comprises a plurality of filler cells, wherein the filler cells are spaced at regular intervals and wherein the distance between two filler cells does not exceed a predetermined value.

16. A method of controlling process parameters during manufacture of an integrated circuit, comprising:

providing a standard cell in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit;

wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit;

providing the standard cell within a placement area of the integrated circuit;

providing a measuring structure within boundaries of the standard cell;

providing at least one feature within the measuring structure in at least one of the plurality of material layers and the plurality of mask layers; and

providing measurement results by the measuring structure in order to control process parameters during manufacture of one of the material layers and mask layers.

17. The method of claim 16 , wherein the measuring structure comprises at least one feature of a critical dimension feature, a dense feature, an isolated feature, an overlay feature and a subresolution assist feature.

18. The method of claim 16 , wherein the standard cell is a filler cell, and further comprising placing functional cells within the placement area of the integrated circuit, wherein the filler cell is arranged between functional cells.

19. The method of claim 18 , further comprising:

checking interaction between the measuring structure of the filler cell and an adjacent functional cell; and

removing the measuring structure from the filler cell if the measuring structure interacts with the adjacent functional cell.

20. The method of claim 18 , further comprising:

routing interconnections between functional cells;

checking interaction between the measuring structure of the filler cell and one of the interconnections; and

removing the measuring structure from the filler cell if the measuring structure interacts with the one of the interconnections.

21. A non-transitory computer readable storage medium storing instructions that when executed by a computer cause the computer to perform a method of designing an integrated circuit, the method comprising:

placing a standard cell within a placement area of the integrated circuit, wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell,

wherein the standard cell is formed in a plurality of material layers of the integrated circuit to perform part of a function of the integrated circuit,

wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit,

wherein the measuring structure includes at least one feature that is included in at least one of the plurality of material layers and the plurality of mask layers,

wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.