Snap-to valid pattern system and method
View Patent ↗Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.
1. A method of providing a physical pattern at one of a plurality of layers in a semiconductor integrated circuit, the method comprising the steps of:
creating a representation of the physical pattern at the one of the plurality of layers in the semiconductor integrated circuit, the physical pattern representation corresponding to a valid pattern defined by data;
snapping an invalid pattern defined by other data into the valid pattern, the step of snapping including determining a valid size and a valid position that approximates an invalid size and an invalid position of the invalid pattern, wherein the valid pattern includes at least a valid size and a valid position, and wherein the valid pattern is obtained based upon a plurality of golden cell valid patterns, wherein the plurality of golden cell valid patterns contain every allowable pattern; and
producing, based upon the other data and the determined valid size and valid position, the semiconductor integrated circuit that includes the physical pattern.
2. The method according to claim 1 wherein the valid pattern further includes a valid route, wherein the valid route includes a valid width and a valid long axis position.
3. The method according to claim 1 wherein the valid pattern further includes a valid line end, wherein the valid line end includes a valid width and a valid short end position.
4. The method according to claim 1 wherein the valid pattern further includes a valid size, wherein the valid size includes a valid height and a valid width.
5. The method according to claim 1 wherein the valid pattern further includes a valid position, wherein the valid position includes a valid size and a valid X, Y position.
6. The method according to claim 1 wherein the valid pattern further includes a valid extension of a valid via pattern, wherein the valid extension is a valid distance of an enclosing shape that surrounds a via pattern.
7. The method according to claim 6 wherein the valid pattern further includes a valid enclosure corresponding to the enclosing shape, wherein the valid enclosure includes three shortest distances from the valid via to the enclosing shape.