Failure detection for wire bonding in semiconductors
Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having “good” circuit traces are subjected to thermal stress for less time than for chips identified as having “bad” circuit traces.
1. A method of testing wire bonds for an integrated circuit (IC) chip in an assembly process comprising:
at a data collection system comprising a computer hardware server in communication with a database system over a computer network:
receiving, over the computer network, a collection of failure detection data for one or more test samples of the IC chip obtained during wire bonding in the assembly process;
performing a failure detection process on the collection of failure detection data to evaluate the test samples of the IC chip, the failure detection process comprising:
(a) training a machine learning algorithm using a training dataset comprising at least a portion of the collection of failure detection data stored in the database system;
(b) detecting, by the machine learning algorithm, failure indicators in the test samples of the IC chip based on the collection of failure detection data;
(c) identifying, by the machine learning algorithm, circuit traces on a surface of each test sample of the IC chip as abnormal circuit traces when one or more failure indicators are detected; and
(d) identifying, by the machine learning algorithm, circuit traces on the surface of each test sample of the IC chip as normal circuit traces when no failure indicators are detected; and
(e) identifying, by the machine learning algorithm, test samples of the IC chip that contain no traces identified as abnormal circuit traces as normal IC chips,
wherein trace data for the circuit traces identified as normal circuit traces are stored into a data structure of normal IC chips.
2. The method of claim 1 further comprising segregating abnormal IC chips or subjecting them to additional destructive tests in the assembly process.
3. The method of claim 1 further comprising:
receiving new or updated failure detection data; and
classifying, by the machine learning algorithm, the new or updated failure detection data as either normal trace data or abnormal trace data based on comparing it with the trace data for the normal IC chips stored in the data structure.
4. The method of claim 1 wherein the failure detection data is used to improve throughput of the process or burn-in reduction.
5. The method of claim 1 further comprising performing a manual destructive test on a subset of the test samples of the IC chip in addition to the failure detection process.
6. The method of claim 1 further comprising skipping a destructive test in the assembly process for the normal IC chips.
7. The method of claim 1 further comprising reducing destructive testing in the assembly process for the normal IC chips.
8. The method of claim 7 wherein the destructive testing comprises a burn-in process in a thermal chamber adapted to stress circuit traces in IC chips for failure analysis.
9. The method of claim 8 wherein the burn-in process is reduced by applying the burn-in process to the normal IC chips for less time than for IC chips having abnormal circuit traces.
10. The method of claim 1 wherein the machine learning algorithm is selected from a group of machine learning algorithms consisting of: linear regression, neural network, or support vector algorithm.
11. A system comprising:
a processor;
a database system;
a network interface for communications over a computer network; and
a memory for storing computer code executable by the processor for performing operations for testing wire bonds for an integrated circuit (IC) chip in an assembly process, the operations comprising:
receiving, over the computer network, a collection of failure detection data for one or more test samples of the IC chip that was obtained during wire bonding in the assembly process;
performing a failure detection process on the collection of failure detection data to evaluate the test samples of the IC chip, the failure detection process comprising:
(a) training a machine learning algorithm using a training dataset comprising at least a portion of the collection of failure detection data stored in the database system;
(b) detecting, by the machine learning algorithm, failure indicators in the test samples of the IC chip based on the collection of failure detection data;
(c) identifying, by the machine learning algorithm, circuit traces on a surface of each test sample of the IC chip as abnormal circuit traces when one or more failure indicators are detected; and
(d) identifying, by the machine learning algorithm, circuit traces on the surface of each test sample of the IC chip as normal circuit traces when no failure indicators are detected; and
(e) identifying, by the machine learning algorithm, test samples of the IC chip that contain no traces identified as abnormal circuit traces as normal IC chips,
wherein trace data for the circuit traces identified as normal circuit traces are stored into a data structure of normal IC chips.
12. The system of claim 11 wherein the operations further comprise subjecting abnormal IC chips to additional destructive tests in the assembly process.
13. The system of claim 11 wherein the operation further comprise:
receiving new or updated failure detection data; and
classifying, by the machine learning algorithm, the new or updated failure detection data as either normal trace data or abnormal trace data based on comparing it with the trace data for the normal IC chips stored in the data structure.
14. The system of claim 11 wherein the failure detection data is used to improve throughput of the process or burn-in reduction.
15. The system of claim 11 further comprising performing a manual destructive test on a subset of the test samples of the IC chip in addition to the failure detection process.
16. The system of claim 11 wherein the operations further comprise skipping a manual destructive test in the assembly process for the normal IC chips.
17. The system of claim 11 wherein the operations further comprise reducing destructive testing in the assembly process for the normal IC chips.
18. The system of claim 17 wherein the destructive testing comprises a burn-in process in thermal chamber.
19. The system of claim 18 wherein burn-in is reduced by applying the burn-in process to the normal IC chips for less time than for IC chips having abnormal circuit traces.
20. The system of claim 11 wherein the machine learning algorithm is selected from a group of machine learning algorithms consisting of: linear regression, neural network, or support vector.