USE OF LAYOUT ANALYSIS TO ENABLE EFFICIENT AND EFFECTIVE RANDOM DEFECT INSPECTION USING A VECTOR-MODE E-BEAM INSPECTION MACHINE
A vector e-beam machine for random defect inspection is disclosed. Contrary to traditional wisdom, it is shown that through a careful choice of target locations, vector machines can provide high-throughput and high coverage even when scanning for random defects. Additionally, by not wastefully scanning locations that provide no additional fault observability, charge accumulation on the wafer—a major concern in e-beam scanning—is reduced. In a preferred embodiment, two approaches are combined: 1) Scan/target only at locations where a random failure can be observed. 2) From the defined list of observable locations, scan/target only the points which have the highest efficiency. Use of these and/or other disclosed techniques enables the scanner to target and evaluate a majority of the total observable defects in a single pass.
1 . A method of testing a processed semiconductor wafer, using voltage contrast inspection (VCI), to detect manufacturing defects therein, said process comprising at least the following steps:
(a) performing a computer-assisted layout analysis of the wafer's design to identify features on the wafer where a short or open defect would be observable by VCI;
(b) based on available scanning capacity of a VCI scanner, selecting features corresponding to a subset of the observable short and/or open defects identified in step (a) for targeting by the VCI scanner;
(c) scanning only the selected features to determine the presence or absence of the observable defects selected in step (b);
(d) whereby a the VCI scanner targets and evaluates a majority of the total VCI-observable defects in a single pass.
2 . A method as defined in claim 1 , wherein the layout analysis of step (a) only considers open defects.
3 . A method as defined in claim 2 , wherein the layout analysis ignores redundant segments.
4 . A method as defined in claim 2 , wherein the layout analysis ignores features where a distance from a line end to a via is too short to permit defect detection by VCI.
5 . A method as defined in claim 2 , where the layout analysis ignores features that are not grounded.
6 . A method as defined in claim 1 , wherein the layout analysis of step (a) only considers short defects.
7 . A method as defined in claim 6 , wherein the layout analysis ignores hard grounded features.
8 . A method as defined in claim 6 , wherein the layout analysis ignores features that would be unobservable because of an absence of any brighter neighbor.
9 . A method as defined in claim 1 , further comprising the step of:
(a2) performing a second computer-assisted layout analysis of the wafer's design to identify features on the wafer where a short or open defect would be observable by VCI under reverse biased conditions.
10 . A method, as defined in claim 9 , wherein the layout analyses of steps (a) and (a2) are compared and used to determine whether to scan using normal or reverse bias conditions.
11 . A method, as defined in claim 9 , wherein the layout analyses of steps (a) and (a2) are analyzed to determine which defects to scan using normal bias conditions and which defects to scan using reverse bias conditions.