Method for improving mask layout and fabrication

1. A method for examining aspects of a mask layout design, comprising:

identifying a hot spot in a mask layout design, wherein the hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies;

generating a test structure for the identified hot spot, the test structure defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies;

fabricating the test structure on a test wafer using specified fabrication processes; and

examining the test structure fabricated on the test wafer to identify one or more adjustments to either the one or more feature geometries of the hot spot of the mask layout design or the specified fabrication processes, the one or more adjustments capable of reducing the one or more fabrication deficiencies.

2. A method for examining aspects of a mask layout design as recited in claim 1 , wherein the method is implemented within a process flow for producing a semiconductor chip.

3. A method for examining aspects of a mask layout design as recited in claim 1 , wherein the test structure is further defined to emulate an environment within a vicinity of the feature geometries susceptible to producing one or more fabrication deficiencies within the hot spot.

4. A method for examining aspects of a mask layout design as recited in claim 1 , wherein the fabricating includes defining the test structure on a reticle and using the reticle to render the test structure on the test wafer in a photolithography process.

5. A method for examining aspects of a mask layout design as recited in claim 1 , wherein the fabrication deficiencies include one or more of an open, a short, an unacceptable critical dimension variation, an unacceptable leakage current, an unacceptable timing characteristic, and an unacceptable circuit performance.

6. A method for examining aspects of a mask layout design as recited in claim 1 , wherein the test structure is defined to be electrically testable such that electrical leads can be applied to the test structure to enable one or more of detecting an open, detecting a short, measuring a leakage current, measuring a critical dimension variation, detecting an unacceptable timing characteristic, and detecting an unacceptable circuit performance.

7. A method for examining aspects of a mask layout design as recited in claim 1 , wherein the specified fabrication processes include a plurality of variations of one or more particular fabrication processes, the plurality of variations of the one or more particular fabrication processes being used to fabricate respective instantiations of the test structure.

8. A method for examining aspects of a mask layout design as recited in claim 7 , wherein the one or more particular fabrication processes include one or more of an optical proximity correction process, a reticle enhancement technology process, a photolithography process, an etching process, and a photoresist stripping process.

9. A method for examining aspects of a mask layout design as recited in claim 1 , further comprising:

implementing selected ones of the one or more adjustments within either the one or more feature geometries of the hot spot or the specified fabrication processes.

10. A method for examining aspects of a mask layout design as recited in claim 1 , further comprising:

generating a plurality of variations of the test structure, the plurality of variations accounting for potential adjustments to the feature geometries of the hot spot of the mask layout design; and

fabricating the plurality of variations of the test structure on the test wafer using specified fabrication processes.

11. A method for examining aspects of a mask layout design as recited in claim 10 , further comprising:

examining the plurality of variations of the test structure fabricated on the test wafer to identify one or more adjustments to either the one or more feature geometries of the hot spot or the specified fabrication processes, the one or more adjustments capable of reducing the one or more fabrication deficiencies.

12. A method for examining aspects of a mask layout design as recited in claim 11 , wherein the examining includes performing an electrical measurement, a physical measurement, or both electrical and physical measurements on each variation of the test structure to generate measurement data, the measurement data indicating whether each variation of the test structure when applied to corresponding feature geometries of the hot spot will provide either an acceptable mask layout design of the hot spot or an unacceptable mask layout design of the hot spot.

13. A method for examining aspects of a mask layout design as recited in claim 10 , further comprising:

examining the plurality of variations of the test structure fabricated on the test wafer to identify one or more edges of a process window for the hot spot, wherein the process window defines a domain within which the hot spot is acceptably fabricated, the domain defined by either feature geometries of the hot spot, fabrication processes, or both feature geometries of the hot spot and fabrication processes.

14. A method for examining aspects of a mask layout design, comprising:

identifying a hot spot in a mask layout design, wherein the hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies;

identifying a test structure that is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies; and

examining measurement data corresponding to the test structure having been fabricated on a test wafer using specified fabrication processes, the examining enabling identification of one or more adjustments to reduce the one or more fabrication deficiencies, the one or more adjustments corresponding to either a feature geometry adjustment within the hot spot of the mask layout design, a fabrication process adjustment, or both a feature geometry adjustment within the hot spot of the mask layout design and a fabrication process adjustment.

15. A method for examining aspects of a mask layout design as recited in claim 14 , wherein the method is implemented within a process flow for producing a semiconductor chip.

16. A method for examining aspects of a mask layout design as recited in claim 14 , wherein the test structure as fabricated on the test wafer is defined to emulate an environment within a vicinity of the feature geometries susceptible to producing one or more fabrication deficiencies within the hot spot.

17. A method for examining aspects of a mask layout design as recited in claim 14 , wherein the measurement data corresponding to the test structure represents effects due to either at least one variation in test structure feature geometry, at least one variation in test structure fabrication processes, or variations in both test structure feature geometry and test structure fabrication processes.

18. A method for examining aspects of a mask layout design as recited in claim 17 , wherein the variation in test structure feature geometry includes either a variation in test structure feature dimension, a variation in test structure feature shape, or variations in both test structure feature dimension and test structure feature shape.

19. A method for examining aspects of a mask layout design as recited in claim 17 , wherein the variation in test structure fabrication processes includes either a variation in an optical proximity correction (OPC) process, a variation in a reticle enhancement technology (RET) process, a variation in photolithography process, a variation in etching process, a variation in photoresist stripping process, or a combination of variations in one or more of the OPC process, the RET process, the photolithography process, the etching process, and the photoresist stripping process.

20. A method for examining aspects of a mask layout design as recited in claim 14 , further comprising:

examining measurement data corresponding to the test structure having been fabricated on a test wafer using specified fabrication processes, the examining enabling identification of one or more edges of a process window for the hot spot, wherein the process window defines a domain within which the hot spot is acceptably fabricated, the domain defined by either features geometries of the hot spot, fabrication processes, or both feature geometries of the hot spot and fabrication processes.

21. A computer readable medium including program instructions for examining aspects of a mask layout design, comprising:

program instructions for identifying a hot spot in a mask layout design, wherein the hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies;

program instructions for identifying a test structure that is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies; and

program instructions for examining measurement data corresponding to the test structure having been fabricated on a test wafer using specified fabrication processes, the examining enabling identification of one or more adjustments to reduce the one or more fabrication deficiencies, the one or more adjustments corresponding to either a feature geometry adjustment within the hot spot of the mask layout design, a fabrication process adjustment, or both a feature geometry adjustment within the hot spot of the mask layout design and a fabrication process adjustment.