Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning

1. A test configuration for use in integrated circuit manufacturing, said test configuration comprising a test structure configured to enable electrical testing of misalignment between two sets of conducting features on a semiconductor wafer portion,

wherein said electrical testing of misalignment between two sets of conducting features on a semiconductor wafer portion comprises measurement of a space-sensitive electrical parameter to characterize gaps between features of different sub-patterns on said semiconductor wafer portion,

further configured to enable measurement of combined multiple instances of said space-sensitive electrical parameter to provide an additive signal with increased sensitivity.

2. The test configuration of claim 1 ,

configured to enable combining said features of different sub-patterns in different combinations to get differential signal changes.

3. The test configuration of claim 2 , wherein said combining said features of different sub-patterns in different combinations utilizes a single test structure with a switchable configuration.

4. The test configuration of claim 3 , further including measuring combined multiple instances of said capacitance to provide an additive signal with increased sensitivity, comprising an array of substantially linear features divided into sub-arrays interlaced in a comb pattern.

5. The test configuration of claim 2 , wherein said combining said features of different sub-patterns in different combinations utilizes multiple congruent test structures each configured to combine features of different sub-patterns in a different single configuration.

6. The test configuration of claim 1 , wherein said space-sensitive electrical parameter is capacitance, and wherein said electrical testing of misalignment between two sets of conducting features on a semiconductor wafer portion comprises comparing two sets of capacitances.

7. The test configuration of claim 1 , further comprising a test structure for measuring feature dimensions, thereby improving the accuracy of diagnostics based on said measuring of a space-sensitive electrical parameter;

wherein said test structure for measuring feature dimensions enables electrical measurement of said feature dimensions;

wherein said test structure for measuring feature dimensions is configured such that feature resistances can be measured; and

wherein said test structure for measuring feature resistances is a Kelvin resistance structure.

8. The test structure of claim 7 , wherein said Kelvin structure includes features comprising at least a first and a second line, said first line being in a first sub-pattern, and said second line being in a second sub-pattern.

9. A test configuration for use in integrated circuit manufacturing, said test configuration comprising a test structure configured to enable electrical testing of misalignment between two sets of conducting features on a semiconductor wafer portion, wherein said misalignment of two sets of conducting features on a semiconductor wafer portion arises due to double patterning.

10. A method for electrically determining misalignment between a first set of features in a first sub-pattern and a second set of features in a second sub-pattern on a semiconductor wafer portion, said method comprising the steps of:

performing a first measurement of space-sensitive electrical parameter between two features of said first set of features;

performing a second measurement of said space-sensitive electrical parameter between a feature of said first set of features and a feature of said second set of features;

comparing said first and second

space-sensitive electrical parameter measurements; and

from said comparison of said first and second space-sensitive electrical parameter measurements, calculating said misalignment.

11. The method of claim 10 , wherein said space-sensitive electrical parameter is chosen from the group consisting of: capacitance, leakage current, and electrical parameters sensitive to the space between features.

12. The method of claim 10 , further including the step of electrically measuring feature dimensions of said feature of said first set of features and said feature of said second set of features.

13. The method of claim 12 , wherein said step of electrically measuring feature dimensions of said feature of said first set of features and said feature of said second set of features comprises measuring resistances of said feature of said first set of features and said feature of said second set of features.