IP Library › Assignment 045467/0534
Patent Assignment
Reel/Frame 045467/0534

Assignment of Assignor's Interest

Recorded: 2018-04-06 Pages: 18
Assignors
LAM, STEPHEN
Executed: 2016-04-21
CIPLICKAS, DENNIS
Executed: 2016-04-15
BROZEK, TOMASZ
Executed: 2016-04-20
CHENG, JEREMY
Executed: 2016-05-06
COMENSOLI, SIMONE
Executed: 2016-04-13
DE, INDRANIL
Executed: 2016-04-12
DOONG, KELVIN
Executed: 2016-04-28
EISENMANN, HANS
Executed: 2016-04-26
FISCUS, TIMOTHY
Executed: 2016-04-13
HAIGH, JONATHAN
Executed: 2016-04-13
HESS, CHRISTOPHER
Executed: 2016-04-12
KIBARIAN, JOHN
Executed: 2016-04-18
LEE, SHERRY
Executed: 2016-04-14
LIAO, MARCI
Executed: 2016-04-15
LIN, SHENG-CHE
Executed: 2016-04-28
MATSUHASHI, HIDEKI
Executed: 2016-04-25
MICHAELS, KIMON
Executed: 2016-04-18
O'SULLIVAN, CONOR
Executed: 2016-04-21
RAUSCHER, MARKUS
Executed: 2016-04-26
ROVNER, VYACHESLAV
Executed: 2016-04-13
STROJWAS, ANDRZEJ
Executed: 2016-04-28
STROJWAS, MARCIN
Executed: 2016-04-13
TAYLOR, CARL
Executed: 2016-04-13
VALLISHAYEE, RAKESH
Executed: 2016-04-12
WEILAND, LARG
Executed: 2016-04-21
YOKOYAMA, NOBUHARU
Executed: 2016-04-13
Assignee
PDF SOLUTIONS, INC.
333 W. SAN CARLOS ST., STE 1000, SAN JOSE, CALIFORNIA, 95110
Covered Properties (10)
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Side-to-Side Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Side-to-Side Short Test Areas
Application: 15/936,759 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtainedfrom Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Chamfer Short Test Areas
Application: 15/936,825 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Tip-to-Side Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Tip-to-Side Short, and Corner Short Test Areas
Application: 15/936,934 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Chamfer Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Chamfer Short Test Areas
Application: 15/937,182 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Tip Short or Leakage, at Least One Side-to-Side Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Tip Short, Side-to-Side Short, and Via Open Test Areas
Application: 15/937,356 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Corner Short or Leakage, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Corner Short Test Areas
Application: 15/942,470 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Chamfer Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Tip-to-Side Short, Chamfer Short, and Via Open Test Areas
Application: 15/942,473 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Tip-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Tip-to-Side Short, Corner Short, and Via Open Test Areas
Application: 15/942,475 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Side-to-Side Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained fromNon-Contact Pads Associated with Respective Side-to-Side Short, Corner Short, and Via Open Test Areas
Application: 15/942,483 →
Method for Processing a Semiconductor Wafer Using Non-Contact Electrical Measurements Indicative of at Least One Chamfer Short or Leakage, at Least One Corner Short or Leakage, and at Least One Via Open or Resistance, Where Such Measurements Are Obtained from Non-Contact Pads Associated with Respective Chamfer Short, Corner Short, and Via Open Test Areas
Application: 15/942,485 →
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest Apr 21, 2025
From: PDF SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 070893/0428 →