Patent Assignment
Reel/Frame 021258/0796
Assignment of Assignor's Interest
Recorded: 2008-07-02
Pages: 2
Assignors
AOKI, KATSUSHI
Executed: 2008-05-12
TODA, TAKAHIRO
Executed: 2008-05-12
YAMASAKI, JUNYA
Executed: 2008-05-12
IIDA, SHINICHI
Executed: 2008-05-12
MURAKAMI, HIROKI
Executed: 2008-05-12
Assignee
FUJITSU LIMITED
1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN
Covered Property
(1)
Method of Shield Line Placement for Semiconductor Integrated Circuit, Design Apparatus for Semiconductor Integrated Circuit, and Design Program for Semiconductor Integrated Circuit