IP Library › Assignment 021731/0700
Patent Assignment
Reel/Frame 021731/0700

Assignment of Assignor's Interest

Recorded: 2008-10-27 Received: 2008-10-27 Pages: 10
Assignor
MONTALVO SYSTEMS, INC.
Executed: 2008-04-17
Assignee
SUN MICROSYSTEMS, INC.
4150 NETWORK CIRCLE, SANTA CLARA, CA, 95054, UNITED STATES
Covered Properties (72)
Tuberculosis Vaccines Comprising Antigens Expressed During the Latent Infection Phase
Application: 11/993,199 →
Elastic Power for Read and Write Margins
Memory Device with Split Power Switch and Related Methods
Method and System for Promoting Traces in an Instruction Processing Circuit
Application: 11/782,140 →
Controlling Operation of a Processor According to Execution Mode of an Instruction Sequence
Application: 11/774,583 →
Re-Fetching Cache Memory Enabling Alternative Operational Modes
Application: 11/751,973 →
Re-Fetching Cache Memory Having Coherent Re-Fetching
Application: 11/751,985 →
Re-Fetching Cache Memory Enabling Low-Power Modes
Application: 11/751,949 →
Reduced-Power Memory with Per-Sector Power/Ground Control and Early Address
Application: 11/740,901 →
Reduced-Power Memory with Per-Sector Ground Control
Application: 11/740,892 →
Instruction Sub-Type Tracking Unit
Application: 60/889,547 →
Memory Cells With Power Switch For Write Operations
Application: 60/888,011 →
Split Power Switch For Memory Cells
Application: 60/888,006 →
Prediction of Data Values Read from Memory by a Microprocessor Using a Dynamic Confidence Threshold
Application: 11/645,901 →
Microarchitecture for Compact Storage of Embedded Constants
Application: 11/566,206 →
Executing Functions Determined via a Collection of Operations from Translated Instructions
Application: 11/561,287 →
Trace Optimization via Fusing Operations of a Target Architecture Operation Set
Application: 11/561,274 →
Processor with Optimized Operation Sequences for Basic Block and Multi-Block Trace Caches
Application: 60/866,205 →
Processor with Basic Block and Multi-Block Trace Caches
Application: 60/866,203 →
Flag Management in Processors Enabled for Speculative Execution of Micro-Operation Traces
Application: 11/553,453 →
Flag Management in Processors Enabled for Speculative Execution of Micro-Operation Traces
Application: 11/553,458 →
Method for Early Deallocation of Physical Registers When Shadow Registers Are Used
Application: 60/863,125 →
Flag Management in Processors Enabled for Speculative Execution of Micro-Operation Traces
Application: 11/553,455 →
Exception Handling for Atomic Traces
Application: 60/862,609 →
Trace Cache for Efficient Self-Modifying Code Processing
Application: 11/535,977 →
Efficient Trace Cache Management During Self-Modifying Code Processing
Application: 11/535,971 →
Selective Trace Cache Invalidation for Self-Modifying Code via Memory Aging
Application: 11/535,972 →
Microprocessor with coherent caches for basic blocks and traces
Application: 60/832,822 →
Microprocessor with caches for instructions, basic blocks, and traces
Application: 60/832,848 →
Managing multiple physical core processors to behave as one virtual core processor
Application: 60/832,823 →
Execution Modes Applied to Instruction Sequences
Application: 60/806,786 →
Application-Directed Rank Coalescing for Memory Power Management
Application: 60/804,085 →
Re-fetching Cache Memory
Application: 60/803,367 →
Re-Fetching Cache Memory
Application: 60/747,818 →
Reduced Power Cache Memory With Per-Sector Power Control
Application: 60/747,200 →
Reduced Power Cache Memory With Per-Sector Power Control
Application: 60/746,049 →
Mechanisms for Software (OS) to Control Threads Between Multiple Cores
Application: 11/279,882 →
Improved Prefetch Hardware Efficiency via Prefetch Hint Instructions
Application: 11/279,880 →
Objective-Directed Mechanisms for Software (OS) to Control Thread Migration
Application: 11/279,883 →
Improved Prefetch Hardware Efficiency via Prefetch Hint Instructions
Application: 60/744,592 →
Software-Assisted Thread Migration Between Multiple Cores
Application: 60/744,010 →
Adaptive Computing Ensemble Microprocessor Architecture
Application: 11/277,761 →
Prefetch Hardware Efficiency via Prefetch Hint Instructions
Application: 60/743,560 →
Software-assisted thread migration between multiple cores
Application: 60/781,772 →
Adaptive computing ensemble microprocessor architecture
Application: 60/777,015 →
Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
Application: 60/761,925 →
Power conservation via DRAM access reduction
Application: 60/761,220 →
Adaptive computing ensemble microprocessor architecture
Application: 60/759,484 →
Microprocessor architecture with reconfigurable function units
Application: 60/758,485 →
Extended resource credit scheme to support dynamic reassignment of resources among data producers
Application: 60/757,240 →
Adaptive computing ensemble microprocessor architecture
Application: 60/751,398 →
Software Hint to Specify the Preferred Branch Prediction to Use for a Branch Instruction
Application: 11/306,000 →
Software hint to specify the preferred branch prediction to use for a branch instruction
Application: 60/749,962 →
Microarchitecture for compressed storage of operations with embedded constants
Application: 60/741,724 →
Fusing or register operations, merging, status flag updates, branches
Application: 60/738,225 →
Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
Application: 60/736,736 →
Power conservation via DRAM access reduction
Application: 60/736,632 →
Zero-cycle execution of clear operation and automatic register free
Application: 60/732,438 →
Extend cache operations to provide control over which levels of the hierarchy they apply to
Application: 60/731,784 →
Synchronized register renaming by a master processor and a coprocessor
Application: 60/731,967 →
Instructions giving hints to the hardware prefetcher for more efficient prediction of prefetches
Application: 60/731,969 →
Maintaining memory coherency within a trace cache
Application: 60/731,785 →
Determining the highest priority abort trigger in an atomic trace
Application: 60/731,962 →
Allocation and deallocation of shadow registers used by atomic traces
Application: 60/730,810 →
Checkpointing status flags for atomic traces
Application: 60/730,550 →
Software hint to specify the preferred branch prediction to use for a branch instruction
Application: 60/721,818 →
Efficient trace cache management during self-modifying code processing
Application: 60/721,385 →
Adaptive computing ensemble microprocessor architecture
Application: 60/707,070 →
Field-Programmable Dynamic Logic Array
Application: 10/071,966 →
Dynamic Programmable Logic Array That Can Be Reprogrammed and a Method of Use
Application: 10/054,471 →
Operand File Using Pointers and Reference Counters and a Method of Use
Application: 10/004,338 →
Method and System for Programmable Replacement Mechanism for Caching Devices
Application: 10/045,127 →