Assignment of Assignor's Interest

Recorded: 2008-10-29 Pages: 3

Assignor

YOSHINAGA, HIROKO

Executed: 2008-10-15

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN

Covered Property (1)

Layout designing method for semiconductor device and layout design supporting apparatus for the same

Application: 12/289,490 →

Publication: US 2009/0113370

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.