Assignment of Assignor's Interest

Recorded: 2008-12-17 Pages: 4

Assignor

WARIKAI, TADASHI

Executed: 2008-12-11

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN

Covered Property (1)

Layout design device and layout design method of semiconductor integrated circuit

Application: 12/314,824 →

Publication: US 2009/0164959

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.