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Patent Assignment
Reel/Frame 022398/0993

Assignment of Assignor's Interest

Recorded: 2009-03-16 Pages: 4
Assignors
CHISHTI, ZESHAN A.
Executed: 2008-12-12
ALAMELDEEN, ALAA R.
Executed: 2008-12-12
WILKERSON, CHRIS
Executed: 2008-12-12
WU, WEI
Executed: 2008-12-12
SOMASEKHAR, DINESH
Executed: 2008-12-15
KHELLAH, MUHAMMAD
Executed: 2008-12-15
LU, SHIH-LIEN
Executed: 2008-12-12
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95052
Covered Property (1)
Performing Multi-Bit Error Correction on a Cache Line
Patent: 8,245,111 →
Application: 12/331,255 →
Publication: US 2010/0146368