Assignment of Assignor's Interest

Recorded: 2009-05-14 Pages: 3

Assignor

ITO, KATSUTOSHI

Executed: 2009-05-12

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN

Covered Property (1)

System and method for layout design of integrated circuit

Application: 12/453,559 →

Publication: US 2009/0293033

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.