IP Library › Patent Application 12453559
Patent Application Utility
App. No. 12/453,559 · Confirmation No. 9147

System and method for layout design of integrated circuit

Inventor: Katsutoshi Ito
Abandoned -- Failure to Respond to an Office Action View Publication ↗
⬇ PDF
 Code Description Pages PDF
2011-09-28 ABN Abandonment 2 View
2011-02-16 CTNF Non-Final Rejection 22 View
2011-02-16 892 List of references cited by examiner 1 View
2011-02-16 SRFW Search information including classification, databases and other search related notes 1 View
2011-02-16 1449 List of References cited by applicant and considered by examiner 1 View
2011-02-16 FWCLM Index of Claims 1 View
2011-02-16 BIB Bibliographic Data Sheet 1 View
2011-02-16 SRNT Examiner's search strategy and results 2 View
2009-11-27 NTC.PUB Notice of Publication 1 View
2009-06-09 PD.FILED.E Priority Documents electronically retrieved by USPTO from a participating IP Office 24 View
2009-06-01 APP.FILE.REC Filing Receipt 3 View
2009-05-14 TRNA Transmittal of New Application 8 View
2009-05-14 SPEC Specification 29 View
2009-05-14 CLM Claims 7 View
2009-05-14 ABST Abstract 1 View
2009-05-14 DRW Drawings-only black and white line drawings 7 View
2009-05-14 OATH Oath or Declaration filed 2 View
2009-05-14 TRAN.LET Transmittal Letter 2 View
2009-05-14 136A Authorization for Extension of Time all replies 8 View
2009-05-14 IDS Information Disclosure Statement (IDS) Form (SB08) 1 View
2009-05-14 FOR Foreign Reference 11 View
2009-05-14 FOR Foreign Reference 22 View
2009-05-14 WFEE Fee Worksheet (SB06) 1 View
2009-05-14 WFEE Fee Worksheet (SB06) 1 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
App. No.
12/453,559
Filed
2009-05-14
Pub. No.
US20090293033A1
Examiner
LEE, ERIC D
Art Unit
2825