Assignment of Assignor's Interest

Recorded: 2009-06-15 Pages: 2

Assignor

SAKAKIDANI, AKIHITO

Executed: 2009-04-27

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN

Covered Property (1)

Method of Verifying Layout of Semiconductor Integrated Circuit Device

Application: 12/484,431 →

Publication: US 2009/0319971

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.