Assignment of Assignor's Interest

Recorded: 2009-08-17 Pages: 2

Assignor

USHIYAMA, KENICHI

Executed: 2009-06-15

Assignee

FUJITSU MICROELECTRONICS LIMITED

7-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU, TOKYO, 163-0722, JAPAN

Covered Property (1)

Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus

Application: 12/461,585 →

Publication: US 2009/0313593

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.