Patent Assignment
Reel/Frame 023401/0813
SECURITY AGREEMENT
Recorded: 2009-10-22
Received: 2009-10-22
Pages: 38
Assignor
VITESSE SEMICONDUCTOR CORPORATION
Executed: 2007-10-29
Assignee
WHITEBOX VSC, LTD.
3033 EXCELSIOR BOULEVARD, SUITE 300, MINNEAPOLIS, MN, 55416, UNITED STATES
Covered Applications
(44)
DIFFERENTIAL OPTO-ELECTRONICS TRANSMITTER
App. No. 11/330,497
→
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
App. No. 11/231,320
→
INTEGRATED CIRCUIT IMPLEMENTATION FOR POWER AND AREA EFFICIENT ADAPTIVE EQUALIZATION
App. No. 10/872,307
→
METHOD AND APPARATUS FOR CONFIGURING THE OPERATION OF AN INTEGRATED CIRCUIT
App. No. 10/852,586
→
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED FEC ADAPTIVE EQUALIZATION
App. No. 10/810,271
→
SWITCHING MODE REGULATOR FOR SFP ETHERNET ADAPTOR
App. No. 10/754,250
→
METHOD OF OVERTONE SELECTION AND LEVEL CONTROL IN AN INTEGRATED CIRCUIT CMOS NEGATIVE RESISTANCE OSCILLATOR TO ACHIEVE LOW JITTER
App. No. 10/721,910
→
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
App. No. 10/677,123
→
ON-CHIP CALIBRATED SOURCE TERMINATION FOR VOLTAGE MODE DRIVER AND METHOD OF CALIBRATION THEREOF
App. No. 10/411,993
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SELF-ALIGNED BIPOLAR TRANSISTOR
App. No. 10/364,075
→
APPARATUS AND METHOD FOR INTER-CHIP OR CHIP-TO-SUBSTRATE CONNECTION WITH A SUB-CARRIER
App. No. 10/308,458
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FAST LOCKING CLOCK AND DATA RECOVERY UNIT
App. No. 10/295,276
→
ADJUSTMENT OF A CLOCK DUTY CYCLE
App. No. 10/282,398
→
MULTIPLE CHANNEL ADAPTIVE DATA RECOVERY SYSTEM
App. No. 10/266,383
→
MULTIPLE ELEMENT CONTROLLED OPTICAL COUPLING
App. No. 10/222,341
→
TRANSFORMERLESS ETHERNET CONTROLLER
App. No. 10/189,619
→
DUAL-MIXER LOSS OF SIGNAL DETECTION CIRCUIT
App. No. 10/159,648
→
CONTROL TECHNIQUES AND DEVICES FOR AN OPTICAL SWITCH ARRAY
App. No. 10/150,531
→
PRECISE PHASE DETECTOR
App. No. 10/145,412
→
DATA SWITCHING SYSTEM
App. No. 10/138,496
→
CLOCK AND DATA RECOVERY WITH A FEEDBACK LOOP TO ADJUST THE SLICE LEVEL OF AN INPUT SAMPLING CIRCUIT
App. No. 10/119,545
→
HIGH BANDWIDTH CLOCK BUFFER
App. No. 10/099,668
→
METHOD OF CONTROLLING THE TURN OFF CHARACTERISTICS OF A VCSEL DIODE
App. No. 10/096,739
→
TIME BASED PACKET SCHEDULING AND SORTING SYSTEM
App. No. 10/096,442
→
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
App. No. 10/074,106
→
RZ RECOVERY
App. No. 10/066,982
→
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
App. No. 10/047,166
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SCALABLE CLOCK DISTRIBUTION FOR MULTIPLE CRU ON THE SAME CHIP
App. No. 10/041,888
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AUTOMATIC LOAD BALANCING IN SWITCH FABRICS
App. No. 10/020,491
→
LOW TEMPERATURE ALUMINUM PLANARIZATION PROCESS
App. No. 09/992,743
→
LOW-DENSITY PARITY CHECK FORWARD ERROR CORRECTION
App. No. 10/044,413
→
MONOLITHIC LOSS-OF-SIGNAL DETECT CIRCUITRY
App. No. 09/976,511
→
PRECISION ON-CHIP TRANSMISSION LINE TERMINATION
App. No. 09/974,451
→
ACTUATOR-CONTROLLED MIRROR WITH Z-STOP MECHANISM
App. No. 09/956,609
→
PROGRAMMABLE ANALOG TAPPED DELAY LINE FILTER HAVING CASCADED DIFFERENTIAL DELAY CELLS
App. No. 09/955,563
→
OUTPUT DRIVER FOR HIGH SPEED ETHERNET TRANSCEIVER
App. No. 09/894,388
→
LIMITING AMPLIFIER MODULATOR DRIVER
App. No. 09/892,807
→
TRANSPARENT TRANSPORT OVERHEAD MAPPING
App. No. 09/882,582
→
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
App. No. 09/878,054
→
PRODUCT CODE BASED FORWARD ERROR CORRECTION SYSTEM
App. No. 09/874,158
→
REDUCED GMII WITH INTERNAL TIMING COMPENSATION
App. No. 09/870,394
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CLOCK BUFFER WITH DC OFFSET SUPPRESSION
App. No. 09/865,008
→
PAD CALIBRATION CIRCUIT WITH ON-CHIP RESISTOR
App. No. 09/850,530
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APPARATUS AND METHOD FOR ANGLED COAXIAL TO PLANAR STRUCTURE BROADBAND TRANSITION
App. No. 09/837,615
→