IP Library › Assignment 023461/0135
Patent Assignment
Reel/Frame 023461/0135

Assignment of Assignor's Interest

Recorded: 2009-11-03 Pages: 4
Assignors
SHANG, JUNQIANG
Executed: 2009-10-23
ZHANG, LIANG
Executed: 2009-10-23
WANG, YONG
Executed: 2009-10-23
LIU, XIN
Executed: 2009-10-23
Assignee
INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
Covered Property (1)
High Speed Chip Screening Method Using Delay Locked Loop
Patent: 8,548,773 →
Application: 12/607,576 →
Publication: US 2011/0098977
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Security Agreement Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
Release of Security Interest Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →