Patent Assignment
Reel/Frame 024114/0059
Assignment of Assignor's Interest
Recorded: 2010-02-18
Received: 2010-03-19
Pages: 253
Assignor
SIEMENS AKTIENGESELLSCHAFT
Executed: 1999-03-31
Assignee
INFINEON TECHNOLOGIES AG
ST.-MARTIN-STR. 53, MUNICH, DEX, 81541, GERMANY
Covered Properties
(24)
Integrated Semiconductor Circuit with an Increased Operating Voltage
Application:
10/187,759 →
Computer-Assisted Method for the Parallel Calculation of the Operating Point of Electric Circuits
Application:
10/009,979 →
Integrated Memory with Redundancy and Method for Repairing an Integrated Memory
Application:
09/888,022 →
Capacitor with High-Epsilon Dielectric or Ferroelectric Material Based on the Fin Stack Principle
Application:
09/863,925 →
Field-Effect-Controlled Transistor and Method for Fabricating the Transistor
Application:
09/861,431 →
Memory Cell Configuration
Application:
09/854,259 →
A Method for Preventing Etching-Induced Damage to a Metal Oxide Film by Patterning the Film After a Nucleation Anneal but While Still Amorphous and Then Thermally Annealing to Crystallize
Application:
09/850,585 →
Ferroelectric Transistor and Method for Fabricating It
Application:
09/849,910 →
Substrate Assembly Having a Depression Suitable for an Integrated Circuit Configuration and Method for Its Fabrication
Application:
09/821,853 →
Magnetoresistive memory having elevated interference immunity
Application:
09/821,964 →
Magnetoresistive Memory with a Low Current Density
Application:
09/822,019 →
Decoder Element for Generating an Output Signal Having Three Different Potentials and an Operating Method for the Decoder Element
Application:
09/822,028 →
Decoder Element for Producing an Output Signal Having Three Different Potentials
Application:
09/822,027 →
Integrated memory having a differential sense amplifier
Application:
09/820,235 →
Circuit configuration for generating a reference voltage for reading a ferroelectric memory
Application:
09/817,578 →
Selectively Deactivating a First Control Loop in a Dual Control Loop Circuit During Data Transmission
Application:
09/811,881 →
Ferroelectric Transistor, Use Thereof in a Memory Cell Confuguration and Method of Producing the Ferroelectric Transistor
Application:
09/801,209 →
Magnetoresistive Element and Use Thereof as a Memory Element in a Memory Cell Configuration
Application:
09/801,210 →
Memory System
Application:
09/793,344 →
Memory Cell with a Stacked Capacitor
Application:
09/774,743 →
Lead Frame, Circuit Board with Lead Frame, and Method for Producing the Lead Frame
Application:
09/771,912 →
Memory Configuration Including a Plurality of Resistive Ferroelectric Memory Cells
Application:
09/767,805 →
Memory Configuration Including a Plurality of Resistive Ferroelectric Memory Cells
Application:
09/767,807 →
Ferroelectric Read/Write Memory with Series-Connected Memory Cells (Cfram)
Application:
09/758,300 →