Patent Assignment
Reel/Frame 024170/0300
CHANGE OF NAME
Recorded: 2010-04-01
Received: 2010-04-01
Pages: 12
Assignor
FASL LLC
Executed: 2010-04-01
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, M/S 250, SUNNYVALE, CA, 94088, UNITED STATES
Covered Applications
(64)
RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
App. No. 11/361,277
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METHOD TO IMPROVE YIELD AND SIMPLIFY OPERATION OF POLYMER MEMORY CELLS
App. No. 10/919,872
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TEST STRUCTURE FOR CHARACTERIZING JUNCTION LEAKAGE CURRENT
App. No. 10/919,119
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METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
App. No. 10/896,299
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
App. No. 10/889,424
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ARCHITECTURE FOR GENERATING ADAPTIVE ARBITRARY WAVEFORMS
App. No. 10/885,284
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FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
App. No. 10/883,924
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ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
App. No. 10/869,286
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METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
App. No. 10/860,450
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RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
App. No. 10/812,703
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SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
App. No. 10/795,890
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ELECTROSTATIC DISCHARGE PERFORMANCE OF A SILICON STRUCTURE AND EFFICIENT USE OF AREA WITH ELECTROSTATIC DISCHARGE PROTECTIVE DEVICE UNDER THE PAD APPROACH AND ADJUSTMENT OF VIA CONFIGURATION THERETO TO CONTROL DRAIN JUNCTION RESISTANCE
App. No. 10/758,173
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PROCESS FOR FABRICATION OF SPACER LAYER WITH REDUCED HYDROGEN CONTENT IN SEMICONDUCTOR DEVICE
App. No. 10/731,494
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PROCESS FOR FABRICATION OF NITRIDE LAYER WITH REDUCED HYDROGEN CONTENT IN ONO STRUCTURE IN SEMICONDUCTOR DEVICE
App. No. 10/731,659
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FLASH MEMORY DEVICE AND METHOD OF FABRICATION THEREOF INCLUDING A BOTTOM OXIDE LAYER WITH TWO REGIONS WITH DIFFERENT CONCENTRATIONS OF NITROGEN
App. No. 10/679,774
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METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
App. No. 10/672,093
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MEMORY DEVICE HAVING HIGH WORK FUNCTION GATE AND METHOD OF ERASING SAME
App. No. 10/658,506
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TRENCH SIDE WALL CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
App. No. 10/430,582
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METHOD TO OBTAIN TEMPERATURE INDEPENDENT PROGRAM THRESHOLD VOLTAGE DISTRIBUTION USING TEMPERATURE DEPENDENT VOLTAGE REFERENCE
App. No. 10/431,065
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NON-VOLATILE MEMORY READ CIRCUIT WITH END OF LIFE SIMULATION
App. No. 10/431,320
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PROCESS FOR REDUCING HYDROGEN CONTAMINATION IN DIELECTRIC MATERIALS IN MEMORY DEVICES
App. No. 10/429,447
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ALIGNMENT SYSTEM FOR PLANAR CHARGE TRAPPING DIELECTRIC MEMORY CELL LITHOGRAPHY
App. No. 10/394,565
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MEMORY DEVICE HAVING REVERSE LDD
App. No. 10/387,774
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CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION
App. No. 10/382,726
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METHOD OF FORMATION OF SEMICONDUCTOR RESISTANT TO HOT CARRIER INJECTION STRESS
App. No. 10/359,872
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ONO FABRICATION PROCESS FOR INCREASING OXYGEN CONTENT AT BOTTOM OXIDE-SUBSTRATE INTERFACE IN FLASH MEMORY DEVICES
App. No. 10/358,586
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
App. No. 10/308,518
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MEMORY WITH IMPROVED CHARGE-TRAPPING DIELECTRIC LAYER
App. No. 10/307,189
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GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
App. No. 10/264,387
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METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
App. No. 10/243,792
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PATH GATE DRIVER CIRCUIT
App. No. 10/243,433
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DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
App. No. 10/230,729
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
App. No. 10/223,195
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
App. No. 10/217,821
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METHOD AND SYSTEM FOR PROVIDING A POLYSILICON STRINGER MONITOR
App. No. 10/155,500
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MEMORY MANUFACTURING PROCESS USING BITLINE RAPID THERMAL ANNEAL
App. No. 10/151,576
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
App. No. 10/136,173
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SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
App. No. 10/128,771
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RELACS SHRINK METHOD APPLIED FOR SINGLE PRINT RESIST MASK FOR LDD OR BURIED BITLINE IMPLANTS USING CHEMICALLY AMPLIFIED DUV TYPE PHOTORESIST
App. No. 10/126,326
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MEMORY MANUFACTURING PROCESS USING DISPOSABLE ARC FOR WORDLINE FORMATION
App. No. 10/126,280
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METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
App. No. 10/109,516
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LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
App. No. 10/109,234
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MEMORY WORDLINE HARD MASK
App. No. 10/109,235
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HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
App. No. 10/100,485
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NROM CELL WITH N-LESS CHANNEL
App. No. 10/086,112
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POWER-SAVING MODES FOR MEMORIES
App. No. 10/061,620
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MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
App. No. 10/022,798
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DIE SEAL FOR SEMICONDUCTOR DEVICE MOISTURE PROTECTION
App. No. 09/998,624
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INNOVATIVE METHOD OF HARD MASK REMOVAL
App. No. 10/045,354
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DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD
App. No. 09/999,869
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DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES
App. No. 09/928,059
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VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES
App. No. 09/915,018
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SOURCE DRAIN IMPLANT DURING ONO FORMATION FOR IMPROVED ISOLATION OF SONOS DEVICES
App. No. 09/893,279
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
App. No. 09/892,431
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Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells
App. No. 09/884,583
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METHODS AND APPARATUS FOR READING A CAM CELL USING BOOSTED AND REGULATED GATE VOLTAGE
App. No. 09/873,927
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INTEGRAL NAVIGATION KEYS FOR A MOBILE HANDSET
App. No. 09/853,126
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BURST ARCHITECTURE FOR A FLASH MEMORY
App. No. 09/829,518
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SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY
App. No. 09/829,193
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I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
App. No. 09/822,995
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PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
App. No. 09/810,155
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DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
App. No. 09/809,969
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PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
App. No. 09/798,667
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FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
App. No. 09/772,600
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