Patent Assignment
Reel/Frame 025438/0357
Assignment of Assignor's Interest
Recorded: 2010-12-02
Pages: 2
Assignor
CELESTRY DESIGN TECHNOLOGIES, INC.
Executed: 2004-02-27
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
Patent:
6,304,097 →
Application:
09/757,067 →