IP Library › Granted Patent US 6,304,097
Granted Patent Utility
US 6,304,097 · Confirmation No. 7865

System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances

Inventor: James C. Chen
Patented Case View Patent ↗
⬇ PDF
 Code Description Pages PDF
2001-01-08 TRNA Transmittal of New Application 3 View
2001-01-08 SPEC Specification 13 View
2001-01-08 CLM Claims 14 View
2001-01-08 ABST Abstract 1 View
2001-01-08 DRW Drawings-only black and white line drawings 4 View
2001-01-08 OATH Oath or Declaration filed 2 View
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Quick Facts
Patent No.
US 6,304,097
App. No.
09/757,067
Filed
2001-01-08
Granted
2001-10-16
Art Unit
2858
PTA
0 days