Patent Assignment
Reel/Frame 026233/0884
Change of Name
Recorded: 2011-05-05
Received: 2011-05-05
Pages: 3
Assignor
PHILIPS SEMICONDUCTORS INTERNATIONAL B.V.
Executed: 2006-09-29
Assignee
NXP B.V.
HIGH TECH CAMPUS 60, EINDHOVEN, NLX, 5656 AG, NETHERLANDS
Covered Properties
(18)
Cache with Prefetch
Application:
11/719,399 →
Method and Related Device for Use in Decoding Executable Code
Application:
10/585,801 →
Memory-Efficient Instruction Processing Scheme
Application:
10/583,052 →
Intergrated Circuit and a Method of Cache Remapping
Application:
10/570,290 →
Processing of a Compileable Computer Program
Application:
10/552,777 →
Reducing Cache Effects of Certain Code Pieces
Application:
10/546,757 →
Using a cache miss pattern to address a stride prediction table
Application:
10/535,591 →
Data Processing Apparatus Address Range Dependent Parallelization of Instructions
Application:
10/530,495 →
Dynamically Controlling Execution of Operations Within a Multi-Operation Instruction
Application:
11/099,231 →
Register Systems and Methods for a Multi-Issue Processor
Application:
10/511,512 →
Communication Path to Each Part of Distributed Register File from Functional Units in Addition to Partial Communication Network
Application:
10/509,562 →
Rerouting Vliw Instructions to Accommodate Execution Units Deactivated Upon Detection by Dispatch Units of Dedicated Instruction Alerting Multiple Successive Removed Nops
Application:
10/496,537 →
Translation lookaside buffer
Application:
10/242,785 →
Processor Prefetch to Match Memory Bus Protocol Characteristics
Application:
10/226,158 →
Instruction Cache Way Prediction for Jump Targets
Application:
10/218,074 →
Memory Region Based Data Pre-Fetching
Application:
10/136,732 →
Fast and Accurate Cache Way Selection
Application:
09/887,463 →
Cache Way Prediction Based on Instruction Base Register
Application:
09/805,384 →