CACHE WITH PREFETCH
A prefetch bit ( 126 ) is associated with cache block ( 125 ) of a cache ( 120 ), and the management ( 130 ) of cache-prefetch operations is based on the state of this bit ( 126 ). Further efficiencies are gained by allowing each application to identify memory areas ( 115 ) within which regularly repeating memory accesses are likely, such as frame memory in a video application. For each of these memory areas ( 115 ), the application also identifies a likely stride value, such as the line length of the data in the frame memory. Pre-fetching is limited to the identified areas ( 115 ), and the prefetch bit ( 126 ) is used to identify blocks ( 125 ) from these areas and to limit repeated cache hit/miss determinations.
1 . A processing system comprising: a processor that is configured to receive data from a memory, a cache, operably coupled between the processor and the memory, that is configured to receive data from the memory and transfer the data to the processor, and a prefetch controller, operably coupled to the cache, that is configured to identify prefetch data that is to be transferred from the memory to the cache, based on a state of a prefetch parameter associated with the data that was received from the memory.
2 . The processing system of claim 1 , further including the memory.
3 . The processing system of claim 1 , wherein the prefetch parameter is a binary digit that identifies whether the processor is likely to request a data item of the prefetch data.
4 . The processing system of claim 3 , wherein the state of the prefetch parameter is based on whether the data from the memory is from one or more defined prefetching area of the memory.
5 . The processing system of claim 1 , wherein identifying the prefetch data is also based on a stride value associated with the data that was received from the memory.
6 . The processing system of claim 5 , wherein the stride value is associated with a defined prefetching area of the memory.
7 . The processing system of claim 5 , wherein the stride value is determined based on prior accesses to the data that was received from the memory.
8 . A cache system comprising: a cache memory comprising a plurality of cache blocks, a prefetch controller, operably coupled to the cache memory, that is configured to transfer prefetch data to the cache memory from an external memory, based on a prefetch parameter associated with each block of the plurality of cache blocks.
9 . The cache system of claim 8 , wherein the prefetch parameter is a binary digit that indicates whether a processor that is operably coupled to the cache system is likely to request a data item in the prefetch data.
10 . The cache system of claim 8 , wherein a state of the prefetch parameter is based on whether the corresponding block is transferred from a defined prefetching area of the external memory.
11 . The cache system of claim 10 , wherein the cache system identifies the prefetch data based on a stride value associated with the defined prefetching area of the external memory.
12 . A method of transferring prefetch data from an external memory to a cache, comprising: receiving a request for a data item from a processor, identifying a cache block of the cache that contains the data item, transferring the prefetch data to the cache based on a state of a prefetch parameter associated with the cache block.
13 . The method of claim 12 , further including: if the data item is not located within the cache, transferring a block of data from the external memory to the cache block.
14 . The method of claim 12 , wherein transferring the prefetch data to the cache is further based on whether the block of data is associated with a defined prefetching area of the external memory.
15 . The method of claim 12 , wherein the state of the prefetch parameter is based on whether the block of data is associated with a defined prefetching area of the external memory.
16 . The method of claim 15 , further including identifying the prefetch data based on a stride value associated with the defined prefetching areas.
17 . The method of claim 12 , further including determining a stride value associated with the block of data from the external memory, and identifying the prefetch data based on the stride value.