IP Library Assignment 026288/0462
Patent Assignment
Reel/Frame 026288/0462

Assignment of Assignor's Interest

Recorded: 2011-05-17 Pages: 3
Assignors
LIN, YU-WEI
Executed: 2011-04-21
HUNG, CHIH-CHIEN
Executed: 2011-04-21
WU, TSANG-YI
Executed: 2011-04-21
Assignee
MEDIATEK INC.
NO. 1, DUSING RD. 1ST, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN
Covered Property (1)
Signal Transmission System with Clock Signal Generator Configured for Generating Clock Signal Having Stepwise/Smooth Frequency Transition and Related Signal Transmission Method Thereof
Patent: 8,619,932 →
Application: 13/109,015 →
Publication: US 2012/0063534
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Dec 17, 2024
From: MEDIATEK INC.
To: INTERLINK SILICON SOLUTIONS INC.
Reel/Frame 069604/0902 →