Patent Assignment
Reel/Frame 069604/0902
Assignment of Assignor's Interest
Recorded: 2024-12-17
Pages: 9
Assignor
MEDIATEK INC.
Executed: 2024-12-06
Assignee
INTERLINK SILICON SOLUTIONS INC.
1891 ROBERTSON ROAD, SUITE 100, OTTAWA, K2H 5B7, CANADA
Covered Properties
(34)
Methods and Systems for Generating Latch Clock Used in Memory Reading
Memory Controller and Memory System
Integrated Circuit with Scan-Based Debugging and Debugging Method Thereof
Methods and Systems for Generating Latch Clock Used in Memory Reading
Memory Controller and Memory System
Method for Tuning Service Performance of Multi-Task System and Multi-Task System Thereof
Beamforming with Global Positioning and Orientation Systems
Memory Controllers and Pad Sequence Control Methods Thereof
Optical Disc Recorder and Buffer Management Method Thereof
Method and an Apparatus for Timing Control of Channel Estimation
Time Shared Rake Fingers and Path Searcher
Shared Filter Design for Pilot Symbol Averaging in Rake Fingers in Wcdma Systems
Memory Circuit and Tracking Circuit Thereof
Method for Mitigating Interference
Protection Setting Method and Protection Releasing Method for Portable Device
Bad Block Identification Methods
Dual Power Rail Word Line Driver and Dual Power Rail Word Line Driver Array
Memory Circuit and Tracking Circuit Thereof
Method and Program for Selective Suspension of Usb Network Device
Low Voltage Transmitter with High Output Voltage
Signal Transmission System with Clock Signal Generator Configured for Generating Clock Signal Having Stepwise/Smooth Frequency Transition and Related Signal Transmission Method Thereof
Control Method for Wireless Communications Device Compatible with Universal Serial Bus Mass Storage Device Class Protocol
Data Storing Method and Apparatus Applied to Flash Memory Storage Device
Dram and Access and Operating Method Thereof
Pre-Decoder for Dual Power Memory
Content Addressable Memory and Related Column Repair Method
Method and Program for Selective Suspension of Usb Device
Dram and Access and Operating Method Thereof
Dram and Access and Operating Method Thereof
Memory and Access and Operating Method Thereof
Memory Including Controller for Controlling Access Signals via Memory Buses and Operating Method Thereof
Memory Interface Circuit Having Signal Detector for Detecting Clock Signal
Memory Interface Circuit Capable of Controlling Driving Ability and Associated Control Method
Apparatuses and Methods for Providing a Virtual Input Key
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.