Memory controller and memory system
View Patent ↗A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.
1. A memory controller for a memory device outputting data and a data strobe signal synchronized with the data according to a memory access request, comprising:
a first counter triggered by rising edges of the data strobe signal and generating a first count value;
a second counter triggered by falling edges of the data strobe signal and generating a second count value;
a third counter triggered by rising edges of an internal clock and generating a third count value;
a first buffer using the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential output of the data corresponding to the third count value after a first predetermined period; and
a second buffer using the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential output of the data corresponding to the third count value after the first predetermined period.
2. The memory controller as claimed in claim 1 , wherein the data and the data strobe signal are delayed by a second predetermined period in any intra-media between memory and memory controller.
3. The memory controller as claimed in claim 2 , further comprising a delay circuit operative to delay the data strobe signal by a third predetermined period.
4. The memory controller as claimed in claim 2 , wherein the first predetermined period exceeds the second predetermined period.
5. The memory controller as claimed in claim 1 , wherein the first buffer comprises a plurality of first buffer entries indexed by sequential integral index.
6. The memory controller as claimed in claim 5 , wherein the first buffer stores the data corresponding to the rising edges of the data strobe signal to the first buffer entries with corresponding index.
7. The memory controller as claimed in claim 5 , wherein the first buffer outputs data from the first buffer entries with the index corresponding to the third count value.
8. The memory controller as claimed in claim 1 , wherein the second buffer comprises a plurality of second buffer entries indexed by sequential integral index.
9. The memory controller as claimed in claim 8 , wherein the second buffer stores the data corresponding to the falling edges of the data strobe signal to the second buffer entries with corresponding index.
10. The memory controller as claimed in claim 8 , wherein the second buffer outputs data from the second buffer entries with the index corresponding to the third count value.
11. A memory system, comprising:
a memory device operative to output data and data strobe signals synchronized with the data according to a memory access request;
a memory controller operative to provide the memory access request, comprising:
a first counter triggered by rising edges of the data strobe signal and generating a first count value;
a second counter triggered by falling edges of the data strobe signal and generating a second count value;
a third counter triggered by rising edges of an internal clock and generating a third count value;
a first buffer using the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential output of the data corresponding to the third count value after a first predetermined period; and
a second buffer using the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential output of the data corresponding to the third count value after the first predetermined period.
12. The memory system as claimed in claim 11 , wherein the data and the data strobe signal are delayed by a second predetermined period in any intra-media between memory and memory controller.
13. The memory system as claimed in claim 12 , further comprising a delay circuit operative to delay the data strobe signal by a third predetermined period.
14. The memory system as claimed in claim 12 , wherein the first predetermined period exceeds the second predetermined period.
15. The memory system as claimed in claim 11 , wherein the first buffer comprises a plurality of first buffer entries indexed by sequential integral index.
16. The memory system as claimed in claim 15 , wherein the first buffer stores the data corresponding to the rising edges of the data strobe signal to the first buffer entries with corresponding index.
17. The memory system as claimed in claim 15 , wherein the first buffer outputs data from the first buffer entries with the index corresponding to the third count value.
18. The memory system as claimed in claim 11 , wherein the second buffer comprises a plurality of second buffer entries indexed by sequential integral index.
19. The memory system as claimed in claim 18 , wherein the second buffer stores the data corresponding to the falling edges of the data strobe signal to the second buffer entries with corresponding index.
20. The memory system as claimed in claim 18 , wherein the second buffer outputs data from the second buffer entries with the index corresponding to the third count value.