Integrated circuit with scan-based debugging and debugging method thereof
View Patent ↗An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.
1. A debugging system, comprising:
a test interface;
a circuit-under-debugging, comprising a scan chain and a plurality of sequential elements, the scan chain capable of shifting states of each of the sequential elements out of the circuit-under debugging;
a memory for receiving and storing the states;
a processing unit for receiving an interrupt when a predetermined condition is met;
a scan-based debugging device coupled between the circuit-under-debugging, the processing unit and the memory for performing a scan operation on the circuit-under-debugging upon the interrupt from the processing unit; and
an embedded in-circuit emulator for dumping the states out of the debugging system via the test interface according to the scan operation, wherein the circuit-under-debugging and the embedded in-circuit emulator are in an integrated circuit,
wherein states of each of the sequential elements are shifted according to the scan operation.
2. The debugging system of claim 1 , wherein the scan-based debugging device comprises a scan-based debugging controller, and when the predetermined condition is met, the scan-based debugging controller enters a scan mode.
3. The debugging system of claim 2 , wherein the scan-based debugging controller is triggered to enter the scan mode by a signal from a host controller, the host controller being outside the integrated circuit.
4. The debugging system of claim 3 , wherein the host controller is a personal computer.
5. The debugging system of claim 2 , wherein the scan-based debugging controller is triggered to enter the scan mode when meeting the predetermined condition programmed in the SBD controller.
6. The debugging system of claim 1 , wherein the scan-based debugging device comprises a clock generator which provides a clock to the circuit-under debugging according to a mode theref.
7. The debugging system of claim 6 , wherein at a normal mode, the clock is a normal clock.
8. The debugging system of claim 6 , wherein at a scan mode, the clock is a scan clock.
9. The debugging system of claim 6 , wherein the clock generator is capable of freezing the circuit-under-debugging by suspending at least one normal clock at a normal mode.
10. The debugging system of claim 1 , wherein the scan-based debugging device comprises a memory interface coupled between the memory and the scan chain.
11. The debugging system of claim 1 , wherein the test interface is a JTAG interface.
12. The debugging system of claim 1 , wherein the test interface is an RS232 interface.
13. The debugging system of claim 1 , wherein the memory is a SRAM.
14. The debugging system of claim 1 , wherein the sequential elements are flip flops.
15. The debugging system of claim 1 , wherein the sequential elements are latches.
16. The debugging system of claim 1 , wherein the memory is in the integrated circuit.
17. The debugging system of claim 1 , wherein the memory is out of the integrated circuit.
18. A scan-based debugging method of an integrated circuit, comprising:
freezing operation of the integrated circuit at a normal function mode according to an interrupt when a predetermined condition is met;
performing a scan operation on a circuit-under-debugging upon the interrupt;
shifting states of a plurality of nodes out of the circuit-under-debugging with a scan chain according to the scan operation, wherein the circuit-under-debugging is in the integrated circuit;
storing the states of the nodes in a memory; and
transferring the states of the nodes to a host controller via a test interface by an embedded in-circuit emulator, wherein the embedded in-circuit emulator is in the integrated circuit.
19. The scan-based debugging method of an integrated circuit of claim 18 , wherein before being shifted out of the circuit-under-debugging, the states of the nodes are captured by sequential elements.
20. The scan-based debugging method of an integrated circuit of claim 19 , wherein the sequential elements are flip flops.
21. The scan-based debugging method of an integrated circuit of claim 19 , wherein the sequential elements are latches.
22. The scan-based debugging method of an integrated circuit of claim 18 , further comprising:
when the predetermined condition is met, having a scan-base debugging controller in the integrated circuit enter a scan mode.
23. The scan-based debugging method of an integrated circuit of claim 22 , wherein the step of entering the scan mode is triggered by a signal from a host controller, the host controller being outside the integrated circuit.
24. The scan-based debugging method of an integrated circuit of claim 22 , wherein the step of entering the scan mode is triggered by meeting the predetermined condition programmed in the scan-base debugging controller.
25. The scan-based debugging method of an integrated circuit of claim 24 , wherein the predetermined condition corresponds to an error condition of the circuit-under-debugging.
26. The scan-based debugging method of an integrated circuit of claim 18 , wherein the test interface is a JTAG interface.
27. The scan-based debugging method of an integrated circuit of claim 18 , wherein the test interface is an RS 232 interface.
28. The scan-based debugging method of an integrated circuit of claim 18 , wherein the memory is a SRAM.
29. The scan-based debugging method of an integrated circuit of claim 18 , wherein the memory is in the integrated circuit.
30. The scan-based debugging method of an integrated circuit of claim 18 , wherein the memory is out of the integrated circuit.