Methods and systems for generating latch clock used in memory reading

1. A method for generating, from an internal clock, a latch clock used in reading a memory, the method comprising:

storing data with a first logic level into a first address of the memory and data with a second logic level into a second address of the memory;

generating a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory;

generating a divided frequency signal by dividing a frequency of the internal clock;

adjusting a phase of the divided frequency signal according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal; and

generating the latch clock according to the delay parameter and the internal clock.

2. The method as claimed in claim 1 , further comprising reading data stored in the memory with reference to the latch clock.

3. The method as claimed in claim 1 , wherein the first memory address and the second memory address are within a page of the memory.

4. The method as claimed in claim 1 , wherein the first memory address and the second memory address are contiguous.

5. The method as claimed in claim 1 , wherein the divided frequency signal has a frequency equal to a frequency of the read data signal.

6. The method as claimed in claim 1 , wherein the frequency of the internal clock is integral times of a frequency of the read data signal.

7. The method as claimed in claim 1 , wherein the read data signal has a frequency equal to integral times of a frequency of the divided frequency signal.

8. The method as claimed in claim 1 , wherein the phase of the divided frequency signal is adjusted by delaying the phase of the divided frequency signal.

9. The method as claimed in claim 8 , wherein as the phase of the divided frequency signal is delayed by a predetermined amount, the delay parameter is set to a mean value of the predetermined amount.

10. A memory subsystem, comprising:

a memory; and

a memory controller comprising an internal clock, the memory controller operative in a calibration mode to store data with a first logic level into a first address of the memory, to store data with a second logic level into a second address of the memory, to generate a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory, to generate a divided frequency signal by dividing a frequency of the internal clock, to adjust a phase of the divided frequency signal according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal, and to generate a latch clock according to the delay parameter and the internal clock.

11. The memory subsystem as claimed in claim 10 , wherein the memory controller reads data stored in the memory with reference to the latch clock in a normal mode.

12. The memory subsystem as claimed in claim 10 , wherein the memory comprises a page, and the first and the second addresses are within the page.

13. The memory subsystem as claimed in claim 10 , wherein the first memory address and the second memory address are contiguous.

14. The memory subsystem as claimed in claim 10 , wherein the divided frequency signal has a frequency equal to a frequency of the read data signal.

15. The memory subsystem as claimed in claim 10 , wherein the frequency of the internal clock is integral times of a frequency of the read data signal.

16. The memory subsystem as claimed in claim 10 , wherein the read data signal has a frequency equal to integral times of a frequency of the divided frequency signal.

17. The memory subsystem as claimed in claim 10 , wherein the phase of the divided frequency signal is adjusted by delaying the phase of the of the divided frequency signal.

18. The memory subsystem as claimed in claim 17 , wherein as the phase of the divided frequency signal is delayed by a predetermined amount, the delay parameter is set to a mean value of the predetermined amount.

19. The memory subsystem as claimed in claim 10 , wherein the memory controller comprises:

a delay element operative to adjust the phase of the divided frequency signal according to the delay parameter;

a phase detector operative to receive the read data signal and the divided frequency signal delayed by the delay element, and to output a phase determined signal in assertion state when at least an edge of the divided frequency signal is aligned with that of the read data signal; and

a control circuit operative to change the delay parameter when the phase determined signal is in deassertion state.

20. A memory subsystem, comprising:

a memory; and

a memory controller providing a latch clock and accessing the memory with reference to the latch clock, comprising:

means for storing data with a first logic level into a first address of the memory, and storing data with a second logic level into a second address of the memory;

means for generating a read data signal by issuing continuous read commands to repeatedly retrieve the data at the first and the second addresses of the memory;

means for generating a divided frequency signal by dividing a frequency of an internal clock;

means for adjusting a phase of the divided frequency signal according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal; and

means for generating the latch clock according to the delay parameter and the internal clock.