Memory controllers and pad sequence control methods thereof
View Patent ↗Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.
1. A memory controller on a single chip, comprising:
a core logic circuit on the single chip, having input/output terminals;
a plurality of input/output (I/O) devices on the single chip, each having a pad; and
a reorderer coupled between the input/output terminals and the input/output devices, wherein the reorderer is programmable to selectively connect the input/output devices to the input/output terminals such that at least two different pad sequences, each communicating with at least one memory device, can be provided and supported by the single chip.
2. The memory controller of claim 1 , wherein the reorderer is programmed by interconnection layer switching.
3. The memory controller of claim 1 , wherein the reorderer comprises:
a multiplexer connected between the input/output terminals and the input/output devices; and
a register controlling the multiplexer;
wherein the reorderer is programmed by setting the register.
4. The memory controller of claim 1 , wherein the at least two different pad sequences support DDR1 and DDR2 SDRAMs, respectively.
5. The memory controller of claim 1 , wherein the at least one memory device and the single chip is packaged in a multiple chip module or a stacked-die package.
6. The memory controller of claim 1 , wherein the input/output terminals comprise data I/O terminals constantly connected to corresponding pads.
7. A method to optimize the pad sequence of a memory controller, comprising:
providing at least two different preferred trace sequences for two different memory devices;
providing the memory controller on a single chip, the memory controller comprising:
a core logic circuit having input/output terminals;
a plurality of input/output (I/O) devices on the single chip, each having a pad; and
a reorderer coupled between the core logic circuit and the input/output devices, wherein the reorderer is programmable to selectively connect the input/output devices to the input/output terminals; and
programming the reorderer to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.
8. The method of claim 7 , wherein programming utilizes interconnection layer switching.
9. The method of claim 7 , wherein the reorderer comprises:
a multiplexer connected between the input/output terminals and the input/output devices; and
a register controlling the multiplexer;
wherein the reorderer is programmed by setting the register.
10. The method of claim 7 , wherein the different memory devices comprise DDR1 and DDR2 SDRAMs.
11. The method of claim 7 , further comprising:
packaging the single chip and one of the different memory devices in one package.