Memory controller and memory system
View Patent ↗A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.
1. A memory controller, comprising:
a first counter triggered by a first edge of a data strobe signal and generating a first count value;
a second counter triggered by a first edge of an internal clock and generating a second count value; and
a first buffer using the first count value as a write address for storage of the data corresponding to the first edge of the data strobe signal, and output of the data corresponding to the second count value after a first predetermined period.
2. The memory controller as claimed in claim 1 , wherein the first edge is a rising edge.
3. The memory controller as claimed in claim 1 , wherein the first edge is a falling edge.
4. The memory controller as claimed in claim 1 , wherein the data and the data strobe signal are delayed by a second predetermined period between the memory controller and a memory device controlled by the memory controller.
5. The memory controller as claimed in claim 4 , further comprising a delay circuit operative to delay the data strobe signal by a third predetermined period.
6. The memory controller as claimed in claim 1 , further comprising a third counter triggered by a second edge of the data strobe signal and generating a third count value, the second edge being complementary to the first edge.
7. The memory controller as claimed in claim 4 , wherein the first predetermined period exceeds the second predetermined period.
8. The memory controller as claimed in claim 6 , further comprising a second buffer using the third count value as the write address for storage of the data corresponding to the second edge of the data strobe signal, and output of the data corresponding to the second count value after the first predetermined period.
9. The memory controller as claimed in claim 1 , wherein a memory device outputs data and the data strobe signal synchronized with the data according to a memory access request.
10. A memory controller, comprising:
a first means for counting, triggered by a first edge of a data strobe signal and generating a first count value;
a second means for counting, triggered by a first edge of an internal clock and generating a second count value; and
a first means for storing data at an address determined by the first count value, and outputting data corresponding to the second count value after a first predetermined period.
11. The memory controller as claimed in claim 10 , wherein the first edge is a rising edge.
12. The memory controller as claimed in claim 10 , wherein the first edge is a falling edge.
13. The memory controller as claimed in claim 10 , further comprising a means for delaying the data strobe signal by a second predetermined period.
14. The memory controller as claimed in claim 13 , wherein the first predetermined period exceeds the second predetermined period.
15. The memory controller as claimed in claim 10 , further comprising a third means for counting triggered by a second edge of the data strobe signal, and generating a third count value, the second edge being complementary to the first edge.
16. The memory controller as claimed in claim 15 , further comprising a second means for storing data at an address determined by the third count value, and outputting the data corresponding to the second count value after the first predetermined period.
17. A method of controlling a memory, comprising:
counting first edges of a data strobe signal to generate a first count value;
counting first edges of an internal clock to generate a second count value; and
storing data in a first buffer at an address determined by the first count value, and outputting data corresponding to the second count value from the buffer after a first predetermined period.
18. The method as claimed in claim 17 , further comprising:
counting second edges of the data strobe signal to generate a third count value, the second edge being complementary to the first edge; and
storing data in a second buffer at an address determined by the third count value, and outputting data corresponding to the second count value after the first predetermined period.
19. The method as claimed in claim 18 , wherein the first edge is a rising edge and the second edge is a falling edge.
20. The method claimed in claim 17 , wherein the first edge is a rising edge.