Patent Assignment
Reel/Frame 027789/0450
Assignment of Assignor's Interest
Recorded: 2012-03-01
Received: 2012-03-01
Pages: 14
Assignor
QUICKTURN DESIGN SYSTEMS, INC.
Executed: 2012-02-27
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(31)
System and Method for Providing Compact Mapping Between Dissimilar Memory Systems
Application:
13/396,849 →
System and Method for Providing Compact Mapping Between Dissimilar Memory Systems
Application:
12/491,106 →
System and Method for Providing Compact Mapping Between Dissimilar Memory Systems
Application:
12/426,164 →
System and Method for Analyzing Power Consumption of Electronic Design Undergoing Emulation or Hardware Based Simulation Acceleration
Application:
11/422,314 →
System and Method for Providing Compact Mapping Between Dissimilar Memory Systems
Application:
11/278,794 →
Method and Apparatus for Rewinding Emulated Memory Circuits
Application:
11/377,762 →
Emulation Processor Interconnection Architecture
Application:
11/321,201 →
Extensible Memory Architecture and Communication Protocol for Supporting Multiple Devices in Low-Bandwidth, Asynchronous Applications
Application:
11/141,599 →
System and Method for Providing Flexible Signal Routing and Timing
Application:
11/140,714 →
A System and Method for Validating an Input/Output Voltage of a Target System
Application:
11/140,722 →
System and Method for Resolving Artifacts in Differential Signals
Application:
11/141,141 →
Dynamic Programming of Trigger Conditions in Hardware Emulation Systems
Application:
11/133,819 →
Method and System for Hardware Based Reporting of Assertion Information for Emulation and Hardware Acceleration
Application:
11/062,170 →
System and Method for Ejecting a High Extraction Force Electromechanical Connector
Application:
11/062,047 →
Method of Visualization in Processor Based Emulation System
Application:
11/047,802 →
System and Method for Configuring Communication Systems
Application:
10/992,165 →
System and Method for Identifying Target Systems
Application:
10/992,588 →
Optimized Interface for Simulation and Visualization Data Transfer Between an Emulation System and a Simulator
Application:
10/975,676 →
Logic Multiprocessor for Fpga Implementation
Application:
10/669,095 →
Clustered Processors in an Emulation Engine
Application:
10/459,340 →
Memory Rewind and Reconstruction for Hardware Emulator
Application:
10/373,558 →
Simulation and Timing Control for Hardware Accelerated Simulation
Application:
10/247,186 →
Timing Resynthesis in a Multi-Clock Emulation System
Application:
10/246,788 →
Emulation System with Time-Multiplexed Interconnect
Application:
10/128,178 →
Apparatus for Emulation of Electponic System
Application:
10/107,741 →
Programmable Logic Device Having Integrated Probing Structures
Application:
09/989,774 →
Optimized Emulation and Prototyping Architecture
Application:
09/949,006 →
Memory Circuit for Use in Hardware Emulation System
Application:
09/922,113 →
Hardware-Assisted Design Verification System Using a Packet-Based Protocol Logic Synthesized for Efficient Data Loading and Unloading
Application:
09/879,658 →
PLD with on-chip memory having a shadow register
Application:
09/817,951 →
High Bandwidth 3D Memory Packaging Technique
Application:
09/796,055 →