Patent Assignment
Reel/Frame 028200/0418
Assignment of Assignor's Interest
Recorded: 2012-05-14
Pages: 3
Assignors
KODAMA, CHIKAAKI
Executed: 2012-04-01
NAKAYAMA, KOICHI
Executed: 2012-04-02
KOTANI, TOSHIYA
Executed: 2012-04-03
NOJIMA, SHIGEKI
Executed: 2012-04-05
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO, 105-8001, JAPAN
Covered Property
(1)
Design Method of Wiring Layout, Semiconductor Device, Program for Supporting Design of Wiring Layout, and Method for Manufacturing Semiconductor Device
Application:
13/405,922 →
Publication:
US 2013/0062771