IP Library Assignment 028210/0654
Patent Assignment
Reel/Frame 028210/0654

Assignment of Assignor's Interest

Recorded: 2012-05-15 Pages: 4
Assignors
SATO, HIROYUKI
Executed: 2012-04-24
KIKUTA, HIDEO
Executed: 2012-04-24
Assignees
FUJITSU LIMITED
1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA, 211-8588, JAPAN
FUJITSU SEMICONDUCTOR LIMITED
2-10-23 SHIN-YOKOHAMA, KOHOKU-KU, YOKOHAMA-SHI, KANAGAWA, 222-0033, JAPAN
Covered Property (1)
Changing Abstraction Level of Portion of Circuit Design During Verification
Patent: 8,510,693 →
Application: 13/469,944 →
Publication: US 2012/0317526
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035498/0324 →